BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 361 ASF Support Registers Document 5722-PG101-R
SMBUS DRIVER SELECT REGISTER (OFFSET 0X6C24)
ASF RNG COMMAND REGISTER (0X6C30)
ASF RNG DATA REGISTER (0X6C34)
Table 378: SMBus Driver Select Register (Offset 0x6C24)
Bit Field Description Init Access
31: 1 Reserved – RO
0 Driver Select Set to 1 to enable SM_DATA_OUT and SM_CLK_OUT to
use new SMBus interface.
0R/W
Table 379: ASF RNG Command Register (0x6c30)
Bit Field Description Init Access
31:28 DB Reg Addr Debug register address. SW should always write 0 to this
field, other values are reserved for HW debug purpose.
0R/W
27:8 Warm Ini Warm-up timer initial value. Used by the random
generator. SW should always write 0 to this field, other
values will cause a premature Warm Done (bit 7) to be set.
0R/W
7 Warm Done The random generator initialization is complete. It normally
(depends on the Warm Ini value) takes 2^21 core clocks
from setting load Ini (bit 2) to complete the initialization.
0RO
6 Rnd Vld The 32-bit random number in ASF RNG Data Register (at
offset 0X6C34) is ready. Clear this bit by writing 1 to Upd
Rnd (bit 5).
0RO
5 Upd Rnd Update the 32-bit random data. Writing 1 to this bit triggers
the random generator to start generating a new 32-bit
random number. Self Clear bit.
0R/W
4 Attn Msk Attention Mask. Writing 1 to this bit disables the attention
signaling when Rnd Vld (bit 6) is set.
0R/W
3 Div2 Divide. When configured low, the random number
generation is twice as fast as high.
0R/W
2 Load Ini Load Warm up timer initial value. Writing 1 to this bit clears
the Warm Done (bit 7) and the internal initialization timer
starts incrementing based on the Warm Ini (bit 27:8) value
until the Warm Done is set.
0W2C
1 Rnd En Random generator enable. 0 R/W
0 Rnd Rst Random generator reset. 0 W2C
Table 380: ASF RNG Data Register (0x6C34)
Bit Field Description Init Access
31:0 Rnd32bit 32-bit random number. 0 R
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