BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 387 PCIe Registers Document 5722-PG101-R
WRITE DMA REQUEST UPPER ADDRESS DIAGNOSTIC REGISTER (OFFSET 0X7C10)
WRITE DMA REQUEST LOWER ADDRESS DIAGNOSTIC REGISTER (OFFSET 0X7C14)
5 Lom_configuration This bit is when set indicates that the power
budget for the device is included within the
system power budget. Structure.
• 0 = Enable (NIC)
• 1 = Disable (LOM)
RW Core 1
4 Concate_select This bit is used to control the swapping of the
PCIe device serial number.
RW Core 0
3 Enable UR Status Bit Fix CQ9715
• 1 = UR status bit in the device status
register is set if a memory read or write
occurs to an unmatched base address.
• 0 = UR status bit is not affected by writes to
an unmatched base address.
R/W – 0
2 Enable Vendor Defined Message Fix
CQ9468
• 1 = UR status bit in the device status
register is not set for routing codes 000b,
010b, 011b, and 100b.
• 0 = UR status bit in the device status
register is set for routing codes 000b, 010b,
011b, and 100b.
R/W – 0
1 Enable Fix CQ10907
power_state_write_mem _enable
• 1 = Software can place the device in
D3HOT state via a memory write or a
configuration write cycle.
• 0 = Software can place the device in
D3HOT only via a configuration write.
R/W – 1
0 Reserved – RO – 0
Note: This register is not applicable to the BCM5906 device.
Table 415: Write DMA Request Upper Address Diagnostic Register (Offset 0x7C10)
Bit Field Description Init Access
31:0 Reg_dw_upr_addr Write DMA Request Upper Address (63:32) 0 RO
Note: This register is not applicable to the BCM5906 device.
Table 416: Write DMA Request Lower Address Diagnostic Register (Offset 0x7C14)
Bit Field Description Init Access
31:0 Reg_dw_lwr_addr Write DMA Request Lower Address (31:0) 0 RO
Table 414: Transaction Configuration Register (0x7C04) (Cont.)
Bit Field Description Access Reset Init
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