Broadcom BCM5722 - Table 512: Auxiliary Control Register (Phy_Addr = 0 X1, Reg_Addr = 18 H, Shadow = 111, Misc Control)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 449 Transceiver Registers Document 5722-PG101-R
AUXILIARY CONTROL REGISTER (PHY_ADDR = 0X1, REG_ADDR = 18H, SHADOW = 111,
MISC CONTROL)
Table 512: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 111, Misc Control)
Bit Field Description Init Access
15 Write Enable (Bits 11:3) • 1 = Write bits 14:0.
• 0 = Write bits 14:12 and 2:0.
0R/W SC
14:12 Shadow Register Read
Selector
• 000 = Normal Operation
• 001 = 10 BASE-T Register.
• 010 = Power Control Register
• 011 = Reserved.
• 100 = Misc Test Register 1
• 101 = Misc Test Register 2
• 110 = Reserved.
• 111 = Misc Control Register
000 R/W
11 Packet Counter Mode
• 1 = Receive packet counter.
• 0 = Transmit packet counter.
0R/W
10 Reserved – 0 R/W
9 Force Auto-MDIX Mode
• 1 = Auto-MDIX is enabled when auto-negotiation is
disabled.
• 0 = Auto-MDIX is disabled when auto-negotiation is
disabled.
8 RGMII Timing Mode
• 1 = RGMII RXC delayed timing mode.
• 0 = RGMII RXC/RXD aligned timing mode.
0R/W
7 RGMII Mode N/A 0 R/W
6 RGMII RXER Mode N/A 0 R/W
5 RGMII Out Of Band
Status Disable
• 1 = Send regular data during IPG.
• 0 = Send Out-Of-Band Status info in RGMII mode.
0R/W
4 Reserved 1R/W
3 MDIO All PHY Select
• 1 = All PHY selected during MDIO writes when PHY
address = 00000b.
• 0 = Normal operation.
0R/W
2:0 Shadow Register
Select
The Auxiliary Control Register provides access to eight
registers using a shadow technique. These three bits written
define which set of 13 upper bits are used. No setup is
required. Register reads are determined by the previous write
operation.
• 000 = Normal Operation
• 001 = 10 BASE-T Register.
• 010 = Power Control Register
• 011 = Reserved.
• 100 = Misc Test Register 1
• 101 = Misc Test Register 2
• 110 = Reserved.
• 111 = Misc Control Register
000 R/W