Broadcom BCM5722 - MAC TX FIFO Enqueue Register (Offset 0 X5 Cb8); Table 332: MAC TX FIFO Enqueue Register (Offset 0 X5 Cb8)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 327 Flow-Through Queues Document 5722-PG101-R
MAC TX FIFO ENQUEUE REGISTER (OFFSET 0X5CB8)
A write to this register will add a transmit packet to the tail of the MACTQ FTQ. The host CPU uses this register to send an
ASF message out.
Since the size of TXMBUF FIFO is only 64 entries and MACTQ is 12 bits wide:
• Bits 21:16 from this register are mapped to bits 11:6 of the MACTQ FTQ.
• Bits 5:0 from this register are mapped to bits 5:0 of the MACTQ FTQ.
• Bits 31:22 and 15:6 are ignored.
The TXMBUF cluster for the ASF message is defaulted to the uppermost three TXMBUFs.
4 Reset Send BD Completion
FTQ
Set this bit to reset the Send BD Completion flow through
queue. When set to 0, this flow through queue is ready for
use. This bit is self-clearing.
R/W
3 Reserved – 0 RO
2 Reset DMA High Priority
Read FTQ
Set this bit to reset the DMA High Priority Read flow
through queue. When set to 0, this flow through queue is
ready for use. This bit is self-clearing.
R/W
1 Reset DMA Read Queue
FTQ
Set this bit to reset the DMA Read Queue flow through
queue. When set to 0, this flow through queue is ready for
use. This bit is self-clearing.
R/W
0 Reserved – R/W
Table 332: MAC TX FIFO Enqueue Register (Offset 0x5CB8)
Bit Field Description Init Access
31:16 Head TXMBUF Pointer Specifies the first MBUF of the TXMBUF cluster for the
transmit packet.
0x003D W/O
15:0 Tail TXMBUF Pointer Specifies the last MBUF of the TXMBUF cluster for the
transmit packet.
0x003F W/O
Table 331: FTQ Reset Register (Offset 0x5C00) (Cont.)
Bit Field Description Init Access