Broadcom BCM5722 - Table 47: Device Specific Registers

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 113 Configuration Space Document 5722-PG101-R
The Device Specific registers are shown in the following table.
Indirect Mode
Host software may use indirect mode to access the BCM5722 Ethernet controller resources, without using Memory Mapped
I/O. Indirect mode shadows MAC resources to PCI configuration space registers. These shadow registers can be read/
written by system software through PCI configuration space registers. The BCM5722 Ethernet controller indirect mode
registers expose the following MAC resources:
• Registers
• Local Memory
• Mailboxes
Indirect mode access can be used in conjunction with Standard or Flat Mode PCI access. Indirect mode has no
interdependency on other PCI access modes and is a mode in itself.
Indirect Register Access
Two PCI configuration space register pairs give host software access to the BCM5722 Ethernet controller register block. The
Register_Base_Address register creates a position in the MAC register block. Valid positions range from 0x0000–0x8000
and 0x30000–0x38800 ranges. Access to the register block from 0x8000–0x30000, should be avoided and is not necessary.
The Flat and Standard Modes do map a memory window into the 0x8000–0xFFFF ranges; however, the Memory Indirection
register pair provides a more efficient mechanism to access the BCM5722 Ethernet controller memory block. The
Register_Data register allows host software to read/write, from the indirection position. The Register_Base_Address register
can be perceived as creating a cursor/pointer into the register block. The Register_Data register allows host software to read/
write to the location, specified by the Register_Base_Address. This register pair accesses the BCM5722 Ethernet controller
register block (see Figure 41 on page 114).
Table 47: Device Specific Registers
Register Cross Reference
Miscellaneous Host Control “Miscellaneous Host Control Register (Offset 0x68)” on page 204.
DMA Read/Write Control “DMA Read/Write Control Register (Offset 0x6C)” on page 205.
PCI State “PCI State Register (Offset 0x70)” on page 206.
Register Base Address “Register Base Address Register (Offset 0x78)” on page 209.
Memory Window Base Address “Memory Window Base Address Register (Offset 0x7C)” on page 210.
Register Data “Register Data Register (Offset 0x80)” on page 211.
Memory Window Data “Memory Window Data Register (Offset 0x84)” on page 211.
UNDI Receive BD Standard Producer Ring
Producer Index Mailbox
“UNDI Receive BD Standard Producer Ring Producer Index Mailbox (Offset
0x98)” on page 214.
UNDI Receive Return Ring Consumer Index
Mailbox
“UNDI Receive Return Ring Consumer Index Mailbox (Offset 0xA0)” on
page 214.
UNDI Send BD Producer Index Mailbox “UNDI Send BD Producer Index Mailbox (Offset 0xA8)” on page 214.
Note: Host software must assert the Indirect_Mode_Access bit in the Miscellaneous Host Control register (see
“Miscellaneous Host Control Register (Offset 0x68)” on page 204) to enable indirect mode.
Note: If indirect register access is performed using memory write cycles (i.e., by accessing the
Register_Base_Address and Register_Data registers through memory mapped by the PCI BAR register), as
opposed to PCI configuration write cycles, the host software must insert a read command to the
Register_Base_Address register between two consecutive writes to the Register_Base_Address and
Register_Data registers.