Broadcom BCM5722 - Figure 10: DMA Write Engine

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R DMA Write Page 26
DMA WRITE
WRITE ENGINE
The DMA write engine (see the following figure) activates whenever a host write is initiated by the send or receive data paths.
Figure 10: DMA Write Engine
The DMA write engine de-queues an internal request and performs the following functions:
• Gathers the data from device internal memory into the write DMA FIFO
• DMAs the data to the host memory from the write FIFO
• Performs byte and word swapping
• Interrupts the host using a line or message signaled interrupt
WRITE FIFO
The write FIFO provides elasticity during data movement from device memory to the host memory. The write FIFO absorbs
small delays created by PCIe bus arbitration. The NetXtreme family uses the write FIFO to buffer data, so internal memory
arbitration is efficient. Additionally, the FIFO isolates the PCI clock domain from the device’s clock domain. This reduces
latency on the PCI bus during the write operation (wait states are not inserted while data is fetched from internal memory).
The operation of the write DMA FIFO is transparent to host software.
BUFFER MANAGER
The buffer manager maintains pools of internal memory used in transmit and receive functions. The buffer manager has logic
blocks for allocation, free, control, and initialization of internal memory pools. The receive MAC requests NIC Rx Mbuf
memory so inbound frames can be buffered. The read DMA engine requests the device Tx Mbuf memory for buffering the
packets from host memory before they are sent out on the wire. The DMA write engine requests a small amount of internal
memory for DMA and interrupt operations. The usage of this internal memory is transparent to host software, and does not
affect device/system performance.
text
RX
PCS
RX
RMII
RX
GMII
RX
IO
RX
MAC
Frame
Mod
WOL
Filter
Rx
FIFO
Power
Management
Frame Header #1
Packet Data #1
Frame
Cracker
Checksum
Calculation
Rules
Checker
Statistics
BD Packet #1
NIC
BD Memory
NIC
BufferMemory
Buffer Manager
DMA
Packet Data #1
BD Packet #1
Host Receive Buffe
r
Descriptor Ring
Host Receive Buffe
r
Memory
Write
FIFO