Broadcom BCM5722 - Figure 58: Word Swap Enable Translation on 32-Bit PCI (no Byte Swap); Figure 59: Byte Swap Enable Translation on 32-Bit PCI (no Word Swap); Figure 60: Byte and Word Swap Enable Translation on 32-Bit PCI

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 145 Endian Control (Byte and Word Swapping) Document 5722-PG101-R
If Word Swapping is not enabled, and the host made a 32-bit read request to address 0x08, the four bytes of data returned
on the PCI bus would actually be the NIC Ring Address rather than the Max_Len and Flags fields. This initially might seem
counter-intuitive, but is explained in Figure 57 on page 144. Therefore, if a software driver running on an x86 host (Little
Endian) referenced on-chip data structures as they are defined in the BCM5722 Ethernet controller data sheet, the driver
should set the Enable Endian Word Swap bit. By setting this bit, the translation would be as follows:
Internal Byte Ordering PCI Byte Ordering
Figure 58: Word Swap Enable Translation on 32-Bit PCI (No Byte Swap)
The only side effect for a little endian host that sets the Enable Endian Word Swap bit would be that the driver would have
to perform an additional word swap on any 64-bit fields (e.g., a 64-bit physical address) that were given to the driver by the
Network Operating System (NOS).
Little-endian hosts will not want to set the Enable Endian Byte Swap bit for target accesses. This bit is intended to be used
by big endian systems that needed PCI data (little endian) translated back to big endian format.
The following figures show the translation of data when the Enable Endian Byte Swap bit is set:
Internal Byte Ordering PCI Byte Ordering
Figure 59: Byte Swap Enable Translation on 32-Bit PCI (No Word Swap)
Internal Byte Ordering PCI Byte Ordering
Figure 60: Byte and Word Swap Enable Translation on 32-Bit PCI
31 1615 0 31 1615 0
0x00
88 89 8A 8B 88 89 8A 8B
0x00
0x04
8C 8D 8E 8F 8C 8D 8E 8F
0x04
Note: Some big endian systems automatically do this depending on the architecture of the host’s PCI to memory
interface.
31 16 15 0 31 16 15 0
0x00 88 89 8A 8B 8F 8E 8D 8C 0x00
0x04 8C 8D 8E 8F 8B 8A 89 88 0x04
31 16 15 0 31 16 15 0
0x00 88 89 8A 8B 8B 8A 89 88 0x00
0x04 8C 8D 8E 8F 8F 8E 8D 8C 0x04