Broadcom BCM5722 - Table 381: Auxiliary Smbus Master Status Register (Offset 0 X6 C40)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R ASF Support Registers Page 362
AUXILIARY SMBUS MASTER STATUS REGISTER (OFFSET 0X6C40)
Table 381: Auxiliary SMBus Master Status Register (Offset 0x6C40)
Bit Field Description Init Access
31:8 Reserved – 0 RO
7 CRC/PEC Error
• 0 = No CRC/PEC Error detected.
• 1 = CRC/PEC Error Detected. This bit is set only by
hardware and can be reset by writing a 1 to this
position.
0R/W
6:5 Reserved – 0 RO
4Failed
• 0 = SMBus Attention not caused by KILL bit.
• 1 = Source of the SMBus attention is a failed bus
transaction, set when KILL bit in SMB Master Control
register is set. This bit is set only by hardware and can
be reset by writing a one to this position.
0R/W
3 Bus Collision
• 0 = SMBus Attention not caused by transaction
collision.
• 1 = Source of SMBus Attention was a transaction
collision. This bit is set only by hardware and can be
reset by writing a 1 to this position.
0R/W
2 Device Error
• 0 = SMBus interrupt not caused by transaction error.
• 1 = Source of SMBus interrupt was the generation of a
SMBus transaction error. This bit is set only by
hardware and can be reset by writing a 1 to this
position. Transaction errors are usually caused by:
- Illegal command field
• Unclaimed cycle
• Master device time-out
0R/W
1 SMBus Attention
• 0 = SMBus attention not caused by Master command
completion.
• 1 = Source of SMBus attention was the completion of
the last Master command. This bit is set only by
hardware and can be reset by writing a 1 to this
position.
0R/W
0Master Busy
• 0 = SMBus Controller Master interface is not
processing a command.
• 1 = Indicates that the SMBus controller master
interface is in the process of completing a command.
None of the other SMBus Master registers should be
accessed if this bit is set.
0RO