Broadcom BCM5722 - Write DMA Status Register (Offset 0 X4 C04)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 315 Write DMA Control Registers Document 5722-PG101-R
WRITE DMA STATUS REGISTER (OFFSET 0X4C04)
9 Write DMA Local Memory
Read Longer Than DMA
Length
Attention Enable. Enable Write DMA Local Memory Read
Longer Than DMA Length Attention.
0R/W
8 Write DMA PCI FIFO
Overwrite Attention
Enable
Enable Write DMA PCI FIFO Overwrite Attention (PCI
write longer than DMA length).
0R/W
7 Write DMA PCI FIFO
Underrun Attention Enable
Enable Write DMA PCI FIFO Underrun Attention. 0 R/W
6 Write DMA PCI FIFO
Overrun Attention Enable
Enable Write DMA PCI FIFO Overrun Attention. 0 R/W
5 Write DMA PCI Host
Address Overflow Error
Attention Enable
Enable Write DMA PCI Host Address Overflow Error
Attention.
0R/W
4 Write DMA PCI Parity
Error Attention Enable
Enable Write DMA PCI Parity Error Attention. 0 R/W
3 Write DMA PCI Master
Abort Attention Enable
Enable Write DMA PCI Master Abort Attention. 0 R/W
2 Write DMA PCI Target
Abort Attention Enable
Enable Write DMA PCI Target Abort Attention. 0 R/W
1 Enable This bit controls whether the Write DMA state machine is
active or not. When set to 0, it completes the current
operation and cleanly halts. Until it is completely halted, it
remains 1 when read.
1R/W
0 Reset When this bit is set to 1, the Write DMA state machine is
reset. This is a self-clearing bit.
0R/W
Table 314: Write DMA Status Register (Offset 0x4C04)
Bit Field Description Init Access
31:10 Reserved – 0 RO
9 Write DMA Local
Memory Read Longer
Than DMA Length
Error
Write DMA Local Memory Read Longer Than DMA
Length Error.
0W2C
8 Write DMA PCI FIFO
Overread Error
Write DMA PCI FIFO Overread Error. (PCI read longer
than DMA length)
0W2C
7 Write DMA PCI FIFO
Underrun Error
Write DMA PCI FIFO Underrun Error. 0 W2C
6 Write DMA PCI FIFO
Overrun Error
Write DMA PCI FIFO Overrun Error. 0 W2C
5 Write DMA PCI Host
Address Overflow Error
Write DMA PCI Host Address Overflow Error. A host
address overflow occurs when a single DMA write begins
at an address below a multiple of 4 GB and ends at an
address above the same multiple of 4 GB (i.e., the host
memory address transitions from
0xXXXXXXXX_FFFFFFFF to 0xYYYYYYYY_00000000
in a single write). This is a fatal error.
0W2C
Table 313: Write DMA Mode Register (Offset 0x4C00) (Cont.)
Bit Field Description Init Access