Broadcom BCM5722 - Table 517: Clock Alignment Control Register (Address 1 Ch, Shadow Value 00011)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers Page 456
CLOCK ALIGNMENT CONTROL (PHY_ADDR = 0X1, REG_ADDR = 1CH, SHADOW 00011B)
Write Enable
During a write to this register, setting Clock Alignment register bit 15 to a 1 allows writing to bits [7:0] of this register. For
reading the values of bits [9:0], perform an MDIO write with bit 15 set to a 0 and preferred shadow values in bits [14:10]. The
next MDIO read of register address 1Ch contains the preferred Shadow register values in bits [9:0].
Shadow Register Selector
Bits [14:10] of this register must be set to 00011 to enable read/write to the Clock Alignment register 1Ch.
GTXCLK Clock Delay Enable
Setting bit 9 of MII register 1Ch with shadow value 00011 enables the GTXCLK internal delay. When this bit is cleared, the
GTXCLK delay is bypassed.
Table 517: Clock Alignment Control Register (Address 1Ch, Shadow Value 00011)
Bit Field Description Init Access
15 Write Enable • 1 = Write bits [9:0].
• 0 = Read bits [9:0].
0R/W
14:10 Shadow Register Selector 00011 = Clock Alignment Control register. 00011 R/W
9 GTXCLK Clock Delay Enable
• 1 = Enable GTXCLK delay.
• 0 = Normal mode (bypass GTXCLK delay).
GTXCLKDLY pin R/W
8:0 Reserved Write as 000h, ignore when read. 000h R/W