Broadcom BCM5722 - Table 100: Latency Timer Register (Offset 0 X0 D); Table 101: Header Type Register (Offset 0 X0 E); Table 98: Class Code Register (Offset 0 X09); Table 99: Cache Line Size Register (Offset 0 X0 C)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCI Configuration Registers Page 192
CLASS CODE REGISTER (OFFSET 0X09)
The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specific in the PCI
specification. This field is hardwired to the class code for an Ethernet interface (0x020000).
CACHE LINE SIZE REGISTER (OFFSET 0X0C)
This register does not apply in PCIe systems and is implemented as a read-write field for legacy compatibility purposes only.
It has no impact on any PCIe device functionality.
LATENCY TIMER REGISTER (OFFSET 0X0D)
This register does not apply in PCIe systems.
HEADER TYPE REGISTER (OFFSET 0X0E)
The 8-bit Header Type register identifies the layout of bytes 10h through 3Fh of the Configuration space, as well as whether
this adapter contains multiple functions. This register is always 0x00, which indicates a single function device (Type 0) using
the format specified in the PCI specification.
Table 98: Class Code Register (Offset 0x09)
Bit Field Description Init Access
23:0 Class Code PCI class code for this device. 020000h RO
Table 99: Cache Line Size Register (Offset 0x0C)
Bit Field Description Init Access
7:0 Reserved – 0 R/W
Table 100: Latency Timer Register (Offset 0x0D)
Bit Field Description Init Access
7:0 Reserved – 0000h RO
Table 101: Header Type Register (Offset 0x0E)
Bit Field Description Init Access
7:0 Header Type Identifies this device as having a single function. 0 RO