Broadcom BCM5722 - Table 273: Receive BD Initiator Control Registers; Table 274: Receive Data Initiator Mode Register (Offset 0 X2 C00); Table 275: Receive BD Initiator Status Register (Offset 0 X2 C04)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 289 Receive BD Initiator Control Registers Document 5722-PG101-R
RECEIVE BD INITIATOR CONTROL REGISTERS
RECEIVE BD INITIATOR MODE REGISTER (OFFSET 0X2C00)
RECEIVE BD INITIATOR STATUS REGISTER (OFFSET 0X2C04)
Table 273: Receive BD Initiator Control Registers
Offset Registers
0x2c00–0x2c03 Receive BD Initiator Mode
0x2c04–0x2c07 Receive BD Initiator Status
0x2c08–0x2c0b Reserved
0x2c0c–0x2c0f Receive BD Initiator Local NIC Standard Receive BD Producer Index
0x2c10–0x2c17 Reserved
0x2c18–0x2c1b Standard Receive BD Ring Replenish Threshold
0x2c1c–0x2fff Reserved
Table 274: Receive Data Initiator Mode Register (Offset 0x2C00)
Bit Field Description Init Access
31:3 Reserved – 0 RO
2 Receive BDs available on a
disabled Receive BD ring enable
Attention enable for Receive BDs available on a disabled
Receive BD ring.
R/W
1 Enable This bit controls whether the Receive BD Initiator state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains one when read.
1R/W
0 Reset When this bit is set to 1, the Receive BD Initiator state
machine is reset. This is a self-clearing bit.
0R/W
Table 275: Receive BD Initiator Status Register (Offset 0x2C04)
Bit Field Description Init Access
31:3 Reserved – 0 RO
2 Receive BDs available on a
disabled Receive BD ring status
Host requests to DMA Receive BDs to a disabled ring. RO
1:0 Reserved – 0 RO