Broadcom BCM5722 - Figure 17: Host Coalescing Engine

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 33 Host Coalescing Document 5722-PG101-R
HOST COALESCING
HOST COALESCING ENGINE
The Host Coalescing Engine is responsible for pacing the rate at which the NIC updates the send and receive ring indices
located in host memory space. The completion of a NIC update is reflected through an interrupt on the BCM5722 Ethernet
controller INTA
pin or a Message Signalled Interrupt (MSI). Although update criteria are calculated separately, all updates
occur at once. This is because all of the ring indices are in one status block, and any host update updates all ring indices
simultaneously. The Host Coalescing Engine triggers based on a tick and/or a frame counter.
Figure 17: Host Coalescing Engine
...
DMA
Write
Engine
Status Block
PCIe
Interface
Buffer
Manager
Host
Coalescing
Engine
MSI
Mailbox
I/O
Driver
Host
Interrupt
Controller
IRQ
Write
FIFO
Tick
Counter
BD
Counter
Status
Memory
Host software may
configure line IRQor MSI
MSI
FIFO