BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 339 General Control Registers Document 5722-PG101-R
2 Recv List Placement (other
devices)
Receive list placement FTQ has stalled. 0 RO
1 SW Event 1 SW Event 1 is set. 0 R/W
0 SW Event 0 SW Event 0 is set. 0 R/W
Note: The version of Rx-RISC Event Register shown in Table 347 applies to the BCM5906 only.
Table 347: RX-RISC Event Register (Offset 0x6810)—BCM5906 Only
Bit Field Description Init Access
31 Flash Attn Flash request is done. 0 R/O
30 VPD Attn There is a pending VPD request. 0 R/O
29 Reserved – 0 R/O
28 ROM Attn There is a pending Expansion ROM request. 0 R/O
27 Flow Attn Flow attention 0 R/O
26 Reserved – 0 R/O
25 MAC Attn MAC needs attention. 0 R/O
24 Memory Enable Attn There is a change in state of the memory enable bit in PCI State
register.
0 R/O
23 SW Event 10 SW Event 10 is set. 0 R/W
22 High-priority Mailbox First 32 Mailbox registers have been updated. 0 R/O
21 Low-priority Mailbox Last 32 Mailbox registers have been updated. 0 R/O
20 DMA Attn A DMA channel needs attention. 0 R/O
19 SW Event 9 SW Event 9 is set. 0 R/W
18 Datalink Attn PCIE Datalink layer needs attention. 0 R/O
17 PCIE Phy Attn PCIE Phy layer needs attention. 0 R/O
16:12 Reserved – 0 R/W
11 RX SW Queue Event Receive Software Queue Event. 0 R/W
10 DMA RD Normal Priority DMA read FTQ has stalled. 0 R/O
9 DMA WR Normal Priority DMA write FTQ has stalled. 0 R/O
8 Recv Data Init (Pre DMA) Receive Data and Receive BD initiator FTQ has stalled. 0 R/O
7:5 Reserved – 0 R/W
4 Recv List Selector Recv list selector is nonzero. 0 R/O
3:0 Reserved – 0 R/W
Table 346: RX-RISC Event Register (Offset 0x6810)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757,
BCM5754, BCM5787 Only (Cont.)
Bit Field Description Init Access
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