Broadcom BCM5722 - Table 148: Link Control Register (Offset 0 Xe0); Table 149: Link Status Command Register (Offset 0 Xe2)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Capabilities Page 220
LINK CONTROL REGISTER (OFFSET 0XE0)
LINK STATUS COMMAND REGISTER (OFFSET 0XE2)
Table 148: Link Control Register (Offset 0xE0)
Bit Field Description Init Access
15:9 Reserved – 0 RO
8 clkreq enable
• 1 = Enable clkreq
• 0 = Disable clkreq
0RO,
R/W
a
a. RO when bit 18 of register 0xDC is “0”. R/W when bit 18 of register 0xDC is “1” for BCM5906/BCM5906M A2 and after only.)
7 Extended Synch When this bit is set, it forces extended sync which gives external devices
(such as logic analyzers) additional time to achieve bit and symbol lock.
0R/W
6 Common Clock
Configuration
When this bit is set, it indicates that the link partners are using a common
reference clock.
0R/W
5:4 Reserved – 0 RO
3 Read Completion
Boundary
This value indicates the Read Completion Boundary value (in bytes) of
the upstream root port.
• 0 = 64
• 1 = 128
0R/W
2 Reserved – 0 RO
1:0 Active State Power
Management Control
This value controls the Active State Power Management supported on
this link.
• 0 = Disabled
• 1 = L0s Entry Enabled
• 2 = L1 Entry Enabled
• 3 = L0s and L1 Entry Enabled
0R/W
Table 149: Link Status Command Register (Offset 0xE2)
Bit Field Description Init Access
15:13 Reserved – 0 RO
12 Slot Clock
Configuration
This value indicates that this device uses the same physical reference
clock that the platform provides on the connector.
RO
11:10 Reserved – 0 RO
9:4 Negotiated Link Width This value returns the negotiated link width. The only valid values are 1,
2, 4, 8, 12, 16, and 32.
1RO
3:0 Link Speed This value returns the negotiated link speed. 1 = 2.5 Gbps. 1 RO