Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Self-Test Page 40
SELF-TEST
BIST
The NetXtreme family supports a manually controlled BIST function for use in manufacturing defect detection. This test is
not intended for operation once the chip has been assembled into a NIC application. The BIST operation is controlled by the
Enable BIST bit in the PCI Clock Control register (see “PCI Clock Control Register (Offset 0x74)” on page 207). The BIST
operates only under specific chip conditions. The PCI BIST register (see “BIST Register (Offset 0x0F)” on page 193) cannot
be written by host software—this register is read-only.
JTAG
IEEE 1149-compliant boundary scan JTAG is supported by the NetXtreme family. The IDCODE, BYPASS, EXTEST, and
SAMPLE instructions of the IEEE standard are implemented. These instructions allow each pin on the part to be controlled
and monitored from the JTAG serial interface pins. This industry standard technique allows the connections between the
component die and the circuit board to be tested once the assembly has been built. The standard packaging for the
NetXtreme family does not provide pinout for JTAG. An industry standard BSDL definition of the JTAG implementation is
available from Broadcom Technical Support.
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