Broadcom BCM5722 - Table 127: DMA Read;Write Control Register (Offset 0 X6 C)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 205 Broadcom Vendor-Specific Capabilities Document 5722-PG101-R
DMA READ/WRITE CONTROL REGISTER (OFFSET 0X6C)
The DMA read/write Control register is used to control various DMA and PCI master functions of the device.
0 Clear Interrupt INTA
Setting this bit will clear (de-assert) INTA as long as the
Mask Interrupt bit is not set. If the Mask Interrupt bit is set,
then writing the
Clear Interrupt bit to a 1 will not de-assert
INTA
, however it will clear the internal unmasked interrupt
state, so if INTA
is later unmasked, then the INTA will de-
assert. However, if the
Mask Interrupt bit is then set again,
then INTA
will be asserted again, because the internal
masked state of the interrupt line cannot be cleared by
writing to the
Clear Interrupt bit.
Since this writing to this bit does not unconditionally clear
interrupts, it is recommended that software drivers write
to
Interrupt Mailbox 0
(see “Interrupt Mailbox 0 Register
(Offset 0x200–0x207)” on page 238 for host standard and
flat modes and “Interrupt Mailbox 0 Register (Offset
0x5800–0x5807)” on page 325 for indirect mode) in order
to cleanly clear interrupts.
0W/O
Table 127: DMA Read/Write Control Register (Offset 0x6C)
Bit Field Description Init Access
31 Reserved –
30:29 Write Control Boundary This field sets the write control boundary and has the following
values:
• 00 = Break request on a multiple of a 64-byte boundary
• 01 = Break request on a multiple of a 128-byte boundary
• 1X = No constraint
10b R/W
28:22 Reserved – 0000 R/W
21:19 DMA Write Watermark For PCIe:
• 0 = 32
• 1 = 64
• 2 = 96
• 3 = 128
• 4 = 160
• 5 = 192
• 6 = 224
• 7 = 256
000 R/W
18:0 Reserved – 000 RO
Table 126: Miscellaneous Host Control Register (Offset 0x68) (Cont.)
Bit Field Description Init Access