Broadcom BCM5722 - Table 534: Master;Slave Seed Register (Phy_Addr = 0 X1, Reg_Addr = 1 Dh, Bit 15 = 0); Table 535: PHY Test Register 1 (Phy_Addr = 0 X1, Reg_Addr = 1 Eh)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers Page 480
MASTER/SLAVE SEED REGISTER (PHY_ADDR = 0X1, REG_ADDR = 1DH, BIT 15 = 0)
PHY TEST REGISTER 1 (PHY_ADDR = 0X1, REG_ADDR = 1EH)
Table 534: Master/Slave Seed Register (PHY_Addr = 0x1, Reg_Addr = 1Dh, Bit 15 = 0)
Bit Field Description Init Access
15 Enable Shadow
Register
• 1 = Select Shadow register.
• 0 = Normal operation.
0R/W
14 Master/Slave Speed
Match
• 1 = Seeds match.
• 0 = Seeds don't match.
0RO, LH
13 Link partner Repeater/
DTE Bit
• 1 = Link partner is a repeater/switch device port.
• 0 = Link partner is a DTE device port.
0RO
12 Link Partner Manual M/
S Config Value
• 1 = Link partner is configured as master.
• 0 = Link partner is configured as slave.
0RO
11 Link Partner Manual M/
S Config Enable
• 1 = Link partner manual master/slave configuration
enabled.
• 0 = Link partner manual master/slave configuration
disabled.
0RO
10:0 Local Master/Slave
Seed Value
Returns the automatically generated Master/Slave
random seed.
000h R/W
Table 535: PHY Test Register 1 (PHY_Addr = 0x1, Reg_Addr = 1Eh)
Bit Field Description Init Access
15 CRC Error Count
Visibility
• 1 = Receiver NOT_OK counters (see “Receiver
NOT_OK Counters (PHY_Addr = 0x1, Reg_Addr =
14h)” on page 433) merged into one 16-bit CRC error
counter.
• 0 = Normal operation.
0R/W
14:8 Reserved 0 R/W
7 Manual Swap MDI
State
• 1 = Manual swap MDI state.
• 0 = Normal operation.
0R/W
6:0 Reserved Write as 0, Ignore when read. 0 R/W