BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 317 RX RISC Registers Document 5722-PG101-R
RX RISC REGISTERS
The following RX RISC registers are exposed to host software to provide a mechanism to download firmware binary. The
information in this section is not intended to provide a comprehensive understanding of the RISC architecture.
RX RISC MODE REGISTER (OFFSET 0X5000)
This register controls the operation of the RX RISC and its miscellaneous functions.
Note: RX RISC registers are not applicable to the BCM5906 device.
Table 315: RX RISC Registers
Offset Register
0x5000–0x5003 RX RISC Mode Register
0x5004–0x5007 RX RISC State Register
0x5008–0x501b Reserved
0x501c–0x501f RX RISC Program Counter
0x5020–0x5033 Reserved
0x5034–0x5037 RX RISC Hardware Breakpoint Register
0x5038–0x53ff Reserved
Table 316: RX RISC Mode Register Fields (Offset 0x5000)
Bit Field Description Init Access
31:15 Reserved Always 0. 0 RO
14 Enable register
address trap halt
When set, if the GRC raises the trap signal to this
processor, it will halt. Cleared on reset and Watchdog
interrupt.
0RW
13 Enable memory
address trap halt
When set, if the MA raises the trap signal to this
processor, it will halt. Cleared on reset and Watchdog
interrupt.
0RW
12 Enable Invalid
Instruction Fetch halt
When set, the condition that causes RX RISC state bit 6
to be set, also halts the RX RISC. Set by reset. Cleared
by Watchdog interrupt.
0RW
11 Enable Invalid Data
access halt
When set, the condition that causes RX RISC state bit 5
to be set, also halts the RX RISC. Set by reset. Cleared
by Watchdog interrupt.
0RW
10 Halt RX RISC Set by TX RISC or the host to halt the RX RISC. Cleared
on reset and Watchdog interrupt.
0RW
9 Flush Instruction Cache Self-clearing bit which forces the instruction cache to
flush.
0WO
8 Enable Instruction
Cache prefetch
Enables prefetch logic within the instruction cache. When
disabled only a single cache line is read on a cache miss.
Cleared on reset.
0RW
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