Broadcom BCM5722 - Table 395: NVM Command Register (Offset 0 X7000); Table 396: NVM Status Register (0 X7004 H)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Non-Volatile Memory Interface Registers Page 370
NVM COMMAND REGISTER (OFFSET 0X7000)
NVM STATUS REGISTER (0X7004H)
Table 395: NVM Command Register (Offset 0x7000)
Bit Field Description Init Access
31:28 Policy Error Reports Address Lockout Policy Error violations. 0 RO
27:18 Reserved – 0RO
17 seeprom
reset start
(BCM5906
only.
Write 1 to this bit to start external EEPROM reset sequence. HW checks the START
condition and issues 9 dummy cycles to reset the external EEPROM.
0R/W
Reserved (all
others)
–
16 seeprom
reset done
(BCM5906
only.
A value of “1” signals that external eeprom reset sequence is done. 0 RO
Reserved (all
others)
–
15:9 Reserved – 0RO
8 last When this bit is set, the next command sequence is interpreted as the last one of a
burst and any cleanup work is done. This means that the buffer is written to flash
memory if needed on a write.
0R/W
7 first This bit is passed to the SEE_FSM or SPI_FSM if the pass_mode bit is set. 0 R/W
6 erase The erase command bit. Set high to execute an erase. This bit is ignored if the wr
is clear.
0R/W
5 wr The Write/Not_Read command bit. Set to execute write or erase. 0 R/W
4 doit Command from software to start the defined command. The done bit must be clear
before setting this bit. This bit is self clearing and will remain set while the command
is active.
0R/W
3 done Sequence completion bit that is asserted when the command requested by
assertion of the doit bit has completed. The done bit will be cleared while the
command is in progress. The done bit will stay asserted until doit is reasserted or
the done bit is cleared by writing a 1 to the done bit. The done bit is the FLSH_ATTN
signal.
0WTC
2:1 Reserved – 0RO
0 Reset When set, the entire NVM state machine is reset. This bit is self clearing. 0 R/W
Table 396: NVM Status Register (0x7004H)
Bit Field Description Init Access
31:13 Reserved –
7:4 SEE_FSM State State Machine Values (TBD) 0 RO
7:4 SEE_FSM State State Machine Values (TBD) 0 RO
3:0 SPI_FSM State State Machine Values (TBD) 0 RO