BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 29 System Management Bus Document 5722-PG101-R
SMBus Connector
The SMBus signals were added to the PCI physical connector with a PCI v2.2 Engineering Change Notification (ECN) titled
Addition of the SMBus to the PCI Connector. Prior to this ECN, network card vendors used a two-pin header and twisted
management cable. This solution complicated installation and increased manufacturing costs. Two pins previously marked
reserved on the PCI connector side-A have now been allocated for SMBus signaling. Pin #40 on PCI Side-A is now defined
as the SMBCLK signal. Pin #41 on PCI Side-A is now defined as the SMBDATA signal. These SMBus signals are defined
in both a 3.3V and 5.0V PCI signaling application. The SMBus signals are exempt from a few requirements regarding loading
and pull-ups, and the programmer is encouraged to read the ECN on the PCI SIIG website. The BCM5722 Ethernet
controller’s SMBus interface meets the high power requirements stated in the SMBus 2.2 specification.
SMBus Data Link
The BCM5722 Ethernet controller’s SMBus interface is compliant with the SMBus 2.0 specification. Each transaction
contains a start and stop delimiter. The SMBus interface is very similar to I
2
C with a few differences. For example, SMBus
masters may enumerate the bus and begin a device address resolution; should two devices have a conflicting address. A
start delimiter is detected when the SMBCLK is sampled high and the SMBDATA signal transitions from high to low. A stop
delimiter is detected when the SMBCLK is sampled high and the SMBDATA signal transitions from low to high. See
Figure 12.
Figure 12: SMBus Start and Stop Conditions
An SMBus transaction consists of several phases. A SMBus master starts a transaction by driving SMBDATA low and
keeping SMBCLK high—a start condition. If two masters are driving the SMBus simultaneously, the masters must arbitrate
for the bus. The programmer is encouraged to read section 4.3.2 in the SMBus 2.0 specification. The master that drives
SMBDATA high, yet detects SMBDATA driven low (contention condition) by a second master, loses bus arbitration. The
arbitration may continue into the address/data phases and past the start condition. Both masters may drive the bus low
simultaneously for an indeterminate number of clocks until one master senses bus contention. See Figure 13 on page 30.
Next, a master must transmit the slave address—the target devices, which decode the read/write transaction. There are
reserved slave addresses that should not be used by any SMBus devices. The programmer is encouraged to look at table 4
in section 5.2 of the SMBus 2.0 specification. After the slave address is driven on the bus, the master indicates whether the
transaction is a read or write. The slave device drives an ACK or NAK on the SMBDATA line for the transaction phase. The
master samples the ACK or NAK accordingly. If the master does sample a NAK, then a Stop condition must be generated.
The master must stop/terminate the transaction. See Figure 14 on page 30.
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MBDATA
SMBCLK
SMBCLK Sampled High
SMBCLK Sampled High
SMBDATA Low to High Transitio
SMBDATA High to Low Transition
START
STOP
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