Broadcom BCM5722 - Table 227: Send Data Initiator Status Register (Offset 0 X0 C04); Table 228: Send Data Initiator Statistics Control Register (Offset 0 X0 C08); Table 229: Send Data Initiator Statistics Enable Mask Register (Offset 0 X0 C0 C)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Send Data Initiator Control Registers Page 270
SEND DATA INITIATOR STATUS REGISTER (OFFSET 0X0C04)
SEND DATA INITIATOR STATISTICS CONTROL REGISTER (OFFSET 0X0C08)
SEND DATA INITIATOR STATISTICS ENABLE MASK REGISTER (OFFSET 0X0C0C)
Table 227: Send Data Initiator Status Register (Offset 0x0C04)
Bit Field Description Init Access
31:3 Reserved – 0 RO
2 Stats Overflow Attn A statistics managed by Send Data Initiator has
overflowed.
0RO
1:0 Reserved – 0 RO
Table 228: Send Data Initiator Statistics Control Register (Offset 0x0C08)
Bit Field Description Init Access
31:5 Reserved – 0 RO
4 Reserved – 0 RO
2 Statistics Clear If set, resets local statistics counters to zero. Clears only
masked statistics. Self-clearing when done.
0R/W
1 Reserved – 0 RO
0 Statistics Enable When set, allows the local statistics counters to
increment. When reset, counters hold their values until
next update to the NIC memory. Enables only masked
statistics.
0R/W
Table 229: Send Data Initiator Statistics Enable Mask Register (Offset 0x0C0C)
Bit Field Description Init Access
31:19 Reserved – 0 RO
18:16 Counters Enable Mask Mask controls which statistics can be updated, cleared or
flushed.
Bits 16:18 correspond to DMA Read Queue Full, DMA
High Priority Read Queue Full, and Send Data
Completion Queue Full respectively.
0R/W
Reserved (BCM5906
only)
–0RO
15:1 Reserved – 0 RO
0 Counters Enable Mask Controls whether Class of Service 0 statistics can be
updated, cleared, or flushed.
0R/W