Broadcom BCM5722 - Table 95: Command Register (Offset 0 X04)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCI Configuration Registers Page 190
COMMAND REGISTER (OFFSET 0X04)
The 16-bit Command register is used by the PCI-based host to enable various features of the device. All of the bit positions
are predefined by the PCI specification. Not all bits in this register are implemented.
Table 95: Command Register (Offset 0x04)
Bit Field Description Init Access
15:11 Reserved – 0 RO
10 Interrupt Disable Setting this bit to 1 disables the device from asserting INTA
on the PCI bus. This bit does not affect the internal state of
the INTA
request.
0R/W
9 Fast Back-to-Back
Enable
Enables fast back-to-back transactions to different
devices.This device does not support this capability,
therefore, this bit is hardwired to 0.
0RO
8 System Error Enable Enables system error detection. The device reports
address parity errors when this bit is set if parity error
detection is enabled.
0R/W
7 Stepping Control Controls whether address/data stepping is done. This
device does not do stepping, therefore, this bit is hardwired
to 0.
0RO
6 Parity Error Enable Enables data parity error detection. The device reports
data parity errors when this bit is set.
0R/W
5 VGA Palette Snoop Enables palette snoop on VGA devices. This device does
not support this capability, therefore, this bit is hardwired to
0.
0RO
4 Memory Write and
Invalidate
The BCM5722 Ethernet controller does not support the
MWI command, therefore, this bit should remain cleared to
0.
0RO
3 Special Cycles Enables device to monitor Special Cycles operations. This
device does not support Special Cycles, therefore, this bit
is hardwired to 0.
0RO
2 Bus Master Enables bus mastering. The device will not act as a bus
master until this bit is set.
0R/W
1 Memory Space Enables Memory space accesses. The device will not
respond to Memory accesses until this bit is set.
0R/W
0 I/O Space Enables I/O space accesses. This device does not support
I/O space, therefore, this bit is hardwired to 0.
0RO