Broadcom BCM5722 - Table 33: Receive BD Rules Value;Mask Register

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 67 Receive Return Rings Document 5722-PG101-R
Bit Name R/W Description Default
31 E R/W Enable. Enabled if set to 1 –
30 & R/W And With Next. This rule and next must both be true to match. The class fields
must be the same. A disabled next rule is considered true. Processor activation
bits are specified in the first rule in a series.
–
29 P1 R/W If the rule matches, the processor is activated in the queue descriptor for the
Receive List Placement state machine.
–
28 P2 R/W If the rule matches, the processor is activated in the queue descriptor for the
Receive Data and Receive BD Initiator state machine.
–
27 P3 R/W If the rule matches, the processor is activated in the queue descriptor for the
Receive Data Completion state machine.
–
26 M R/W Mask If set, specifies that the value/mask field is split into a 16-bit value and 16-
bit mask instead of a 32-bit value.
–
25 D R/W Discard Frame if it matches the rule. –
24 Map R/W Map Use the masked value and map it to the class. –
23:18 Reserved R/W Must be set to zero. 0
17:16 Op R/W Comparison Operator specifies how to determine the match:
• 00 = Equal
• 01 = Not Equal
• 10 = Greater than
• 11 = Less Than
–
15:13 Header R/W Header Type specifies which header the offset is for:
• 000: Start of Frame (always valid)
• 001: Start of IP Header (if present)
• 010: Start of TCP Header (if present)
• 011: Start of UDP Header (if present)
• 100: Start of Data (always valid, context sensitive)
• 101–111: Reserved
–
12:8 Class R/W The class this frame is placed into if the rule matches. 0:4, where 0 means discard.
The number of valid classes is the Number of Active Queues divided by the
Number of Interrupt Distribution Groups. Ring 1 has the highest priority and Ring
4 has the lowest priority.
–
7:0 Offset R/W Number of bytes offset specified by the header type. –
Table 33: Receive BD Rules Value/Mask Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mask
1514131211109876543210
Value
Bit Name R/W Description Default
31:16 Mask – – –
15:0 Value – – –