Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R MSI Page 180
To clarify second issue in traditional interrupt scheme, an example is given. The BCM5722 Ethernet controller receives one
or more packets from the networks. The BCM5722 Ethernet controller does the following:
• DMAs data of received packets to the host.
• DMAs receive buffer descriptors to Receive Return Ring in the host memory.
• DMAs status block to the host memory.
• Generates an interrupt to request its device driver for processing.
The writes are posted and are actually performed at some later time by the PCI host bridge. When interrupt service routine
of device driver is executed, the driver reads the status block from the host memory and finds that status block does not
contain latest index information if the writes for status block are not performed by the PCI host bridge yet. The scheme to
resolve this problem is to do a dummy read of the BCM5722 Ethernet controller in the beginning of the interrupt service
routine. The dummy read has to traverse the same bridge that memory writes from the BCM5722 Ethernet controller have
to traverse to get to the host memory. The ordering rules for bridges dictate that the bridge must flush its posted write buffers
before permitting a read to traverse the bridge. As a result, writes for status block are flushed to the host memory by the
bridge before dummy read cycle is completed.
MESSAGE SIGNALED INTERRUPT
A simplified block diagram showing a possible MSI scheme is depicted in Figure 65.
Figure 65: Message-Signaled Interrupt Scheme
BCM5700
PCI Host
Bridge
Host Memory
CPU
Interrupt
Controller
PCI Bus
Host Bus Interrupt
BCM5722
Ethernet
Controller
PCI Host Bridge
Host
Memory
CPU
Interrupt
Controller
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