Broadcom BCM5722 - Figure 45: Memory Window Base Address Register; Table 48: PCI Address Map Standard View

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Configuration Space Page 120
The BCM5722 Ethernet controller resources listed in the following are decoded in the 64K address block.
32K is partitioned for MAC control registers and 32K available for a memory access window. Range 0x0000–0x00FF is a
complete shadow of the PCI configuration space registers—host software can also read/write to the BCM5722 Ethernet
controller’s PCI configuration space registers via the host memory map. Host software may use the shadow registers to
change PCI register contents and avoid PCI configuration cycles (transactions). Again, using the host memory map is slightly
more efficient. The MAC’s control/status registers are mapped from 0x0400–0x8000. See Section 12: “BCM5722 Ethernet
Controller Register Definitions” on page 186 for complete register and bit definitions. Finally, the memory window range is
0x8000–0xFFFF. This 32K window is set in the PCI Configuration space using the Memory_Window_Base_Address register
(see Figure 45). Bits 23:15 set the window aperture and bits 14:2 are effectively ignored/masked off. Bits 14–2 are relevant
when host software uses memory indirection and the Memory_Window_Data register.
Figure 45: Memory Window Base Address Register
Figure 46 shows how the 32K window can float in the BCM5722 Ethernet controller’s local memory. The window aligns on
32K boundaries. For example, the memory window may start on the following addresses: 0x8000, 0x10000, and 0x18000.
The window aperture may be positioned in the internal memory range 0x00000000 to 0x0001FFFF. When host software
reads/writes to PCI_BAR + 32K + OFFSET in the host memory space, the BCM5722 Ethernet controller translates this read/
write access to Memory_Window_Base_Address + OFFSET. Host software must not read/write from any address greater
than PCI_BAR + 64K, since this memory space is not decoded by the BCM5722 Ethernet controller. Such an access may
be decoded by another device, or simply go unclaimed on the PCI bus. Figure 46 on page 121 shows the relationship
between the Memory_Window_Base_Address register and the Memory Window.
Table 48: PCI Address Map Standard View
Offset Name Size
0x00000000–0x000000ff PCI Configuration space 256 bytes
0x00000200–0x000003ff High Priority Mailboxes 512 bytes
0x00000400–0x00007fff BCM5722 Ethernet controller registers 31 KB
0x00008000–0x0000ffff Memory Window 32 KB
Rsvd Window Rsvd
[31:24] [14:2] [1:0]
XXXX (Dont Care)
[23:15]
Window aprerature
set by bits 23-15
These bits are
ignored - 32K windo
w
position.