Broadcom BCM5722 - Table 473: Phy;Serdes Control Override Register (Offset 0 X7 E30)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 411 PCIe Registers Document 5722-PG101-R
PHY/SERDES CONTROL OVERRIDE REGISTER (OFFSET 0X7E30)
4 Fast Symbol Lock Up When this bit is:
• Set to 1, the symbol boundary locks after receiving the first
COM symbol.
• Clear, the symbol boundary locks after receiving four COM
symbols within a 64-symbol time.
0R/W
3 Down Stream Lane Set this bit to change the link to be a downstream lane (or
upstream component).
0R/W
2 Training Bypass Set to bypass link initialization and configuration process. 0 R/W
1 External Loopback Force remote (external) loopback test mode. 0 R/W
0 Internal Loopback Force internal parallel loopback test mode. 0 R/W
Table 473: PHY/SerDes Control Override Register (Offset 0x7E30)
Bit Field Description Init Access
31:18 Reserved 0RO
17 obsvElecIdleValue Override value for the obsvElecIdle signal from SerDes. 0 R/W
16 obsvElecIdleOverride Set to override the obsvElecIdle signal value from SerDes with the
value in bit 17 of this register.
0R/W
15 pllIsUpValue Override value for pllIsUp signal form SerDes. 0 R/W
14 pllIsUpOverride Set to override the pllisUp signal value from SerDes with the value in
bit 15 of this register.
0R/W
13 rcvrDetValue Override value for rcvrDetected signal from SerDes. 0 R/W
12 rcvrDetOverride Set to override the rcvrDetected signal from SerDes with the value in
bit 13 of this register.
0R/W
11:10 rcvrDetTimeControl Time unit of the rcvrDetectionTime:
• 2’b00 = Symbol time.
• 2’b01 = 64 ns.
• 2’b10 = 1 µs.
0x0 R/W
9:0 rcvrDetectionTime Time value that the PHY logical layer uses for timing receiver detection
sequences.
0x3FF R/W
Table 472: PHY Test Control Register (Offset 0x7E2C) (Cont.)
Bit Field Description Init Access