Broadcom BCM5722 - Table 114: Power Management Control;Status Register (Offset 0 X4 C)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCI Power Management Capabilities Page 198
POWER MANAGEMENT CONTROL/STATUS REGISTER (OFFSET 0X4C)
This 16-bit register is used to manage the device’s power management state as well as to enable and monitor PME events.
PMCSR-BSE REGISTER (OFFSET 0X4E)
The PMCSR_BSE (PMCSR PCI to PCI Bridge Support Extensions) register is not implemented in the device.
8:6 Aux Current The device supports the Data Register for reporting Aux
Current requirements so this field is not applicable.
000 RO
5 DSI Indicates that the device requires device specific
initialization (beyond the PCI configuration header) before
the generic class device driver is able to use it. This device
hardwires this bit to 0 to indicate that DSI is not necessary.
0RO
4 Reserved – 0 RO
3 PME Clock Indicates that the device relies on the presence of the PCI
clock for PME
operation. The device does not require the
PCI clock to generate PME
, therefore, this bit is hardwired to
0.
0RO
2:0 Version A value of 010b indicates that this function complies with
revision 1.1 of the PCI Power Management Interface Spec.
The device hardwires this value to 010.
010 RO
Table 114: Power Management Control/Status Register (Offset 0x4C)
Bit Field Description Init Access
15 PME Status This bit is set when the device would normally assert the PME
signal independent of the state of the PME Enable bit.
Writing a 1 to this bit will clear it and cause the device to stop
asserting PME
(if enabled).
0R/W2C
14:13 Data Scale Indicates the scaling factor that is used when interpreting the
value of the Data register (offset 7 in PM capability space).
The device hardwires this value to 1 to indicate a scale of 1x.
1RO
12:9 Data Select Indicates which data is to be reported via the Data register
(offset 7 in PM capability space).
0h R/W
8 PME Enable Enables the device to generate PME
when this bit is set to 1.
When 0, PME
generation is disabled.
1 if VAux is
Present
R/W
7:2 Reserved – 00h RO
1:0 Power State Indicates the current power state of the device when read.
When written, it sets the device into the specified power state.
• 00 = D0
• 01 = D1
• 02 = D2
• 03 = D3
If software attempts to write an unsupported, optional state to
this field, the write operation must complete on the bus;
however, the data is discarded and no state change occurs.
00 R/W
Table 113: Power Management Capabilities Register (Offset 0x4A) (Cont.)
Bit Field Description Init Access