Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers (BCM5906/BCM5906M) Page 508
Acknowledge Complete
This read-only bit returns a 1 after the acknowledgment exchange portion of the auto-negotiation process has been
completed and the arbitrator state machine has exited the Acknowledge Complete state. It remains this value until the auto-
negotiation process is restarted, a link fault occurs, auto-negotiation is disabled, or the PHY is reset.
Acknowledge Detected
This read-only bit is set to 1 when the arbitrator state machine exits the Acknowledge Detected state. It remains high until
the auto-negotiation process is restarted, or the PHY is reset.
Ability Detect
This read-only bit returns a 1 when the auto-negotiation state machine is in the Ability Detect state. It enters this state a
specified time period after the auto-negotiation process begins, and exits after the first FLP burst or link pulses are detected
from the link partner. This bit returns a 0 any time the auto-negotiation state machine is not in the Ability Detect state.
Super Isolate
Writing a 1 to this bit places the PHY core into the super Isolate mode. Similar to the Isolate mode, all TXD0 inputs are
ignored, and all RXD outputs are tri-stated. Additionally, all link pulses are suppressed. This allows the PHY core to coexist
with another PHY on the same adapter card, with only one being activated at any time.
10BASE-T Serial Mode
Writing a 1 to bit 1 of the Auxiliary Mode register enables the 10BASE-T serial mode. Serial operation is not available in
100BASE-X mode
Broadcom Test Register
Shadow Register Enable
Writing a 1 to bit 7 of register 1Fh allowsR/W access to the shadow registers located at addresses 0Fh–1Eh. To access the
default MII registers (register 00h to 1Eh), this bit must be set to 0.
Table 558: Broadcom Test Register (Address 31d, 1Fh)
BIt Name R/W Description Default
15:8 Reserved - - 00h
7 Shadow Register Enable R/W 1 = Enable shadow registers 18h-1Eh
0 = Disable shadow registers
0
6 Reserved - - 0
5 Reserved - - 0
4:0 Reserved - - 0Bh
R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear after read
operation. Use default values of reserved bit(s) when writing to reserved bit(s).
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