Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers Page 418
PHY IDENTIFIER REGISTER (PHY_ADDR = 0X1, REG_ADDRESSES 02H)
PHY IDENTIFIER REGISTER (PHY_ADDR = 0X1, REG_ADDRESSES 03H)
2 Link Status The BCM5722 Ethernet controller returns a 1 on bit 2 of
the MII Status Register when the link monitor is in the Link
Pass state, indicating that a valid link has been
established. Otherwise, it returns a 0. When a link failure
occurs, the Link Status bit is latched at 0 and remains so
until the bit is read, and the BCM5722 Ethernet controller
is in the Link Pass state.
• 1 = Link is up (Link Pass state)
• 0 = Link is down (Link Fail state)
0RO
LL
1 Jabber Detect Jabber detection is performed within the PHY and the
result is latched into this bit. The BCM5722 Ethernet
controller returns a 1 in bit 1 of the status register when a
jabber condition has been detected. The bit is cleared by
the read.
• 1 = Jabber condition detected
• 0 = No jabber condition detected
0RO
LH
0 Extended Capability The BCM5722 Ethernet controller supports extended
capability registers, and returns a 1 when bit 0 of the MII
Status register is read.
• 1 = Extended register capabilities
• 0 = No extended register capabilities
1RO
H
Table 480: PHY Identifier Registers (PHY_Addr = 0x1, Reg_Address 02h)
Bit Field Description Init Access
15:0 Address = 02: ID MSBs 16 MSBs of PHY Identifier (bits
18:3 of unique organization
identifier)
0x0143 (For BCM5722, BCM5755,
BCM5755M, BCM5756M, BCM5757 only)
RO
Table 481: PHY Identifier Registers (PHY_Addr = 0x1, Reg_Address 03h)
Bit Field Description Init Access
15:10 OUI Bits 24:19 of unique organization
identifier
101111b (BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
RO
9:4 Model Device Model Number (Metal
Programmable)
• 101101b (BCM5722, BCM5756M only)
• 001110b (BCM5754, BCM5787 only)
• 001100b (BCM5755 only )
RO
3:0 Revision Device Revision Number (Metal
Programmable)
0000b (For BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
RO
Table 479: MII Status Register (PHY_Addr = 0x1, Reg_Addr = 01h) (Cont.)
Bit Field Description Init Access