Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Ethernet MAC Control Registers Page 256
RECEIVE MAC STATUS REGISTER (OFFSET 0X46C)
This register contains the status of the receive Ethernet interface. Once the interface is initialized, this register is used to
determine the cause of a receive error event.
MAC HASH REGISTER 0–3 (OFFSET 0X470–0X47C)
The hash value provides a way for the MAC to accept multicast frames through a hashing function. If the CRC hash of a
multicast destination address matches a bit in the hash registers, the frame is accepted (see “Packet Filtering” on page 97).
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Table 208: Receive MAC Status Register (Offset 0x46C)
Bit Field Description Init Access
31:4 Reserved – 000000h RO
3 RX FIFO Overrun The RX FIFO has encountered an overrun condition. 0 W2C
2 XON received A MAC Control frame with the PAUSE opcode was
received with the PAUSE TIME field set to zero. The bit is
sticky and must be written to clear.
0W2C
1 XOFF received A MAC Control frame with the PAUSE opcode was
received with the PAUSE TIME field set to nonzero. The bit
is sticky and must be written to clear.
0W2C
0 Remote Transmitter
XOFFed
A previously received XOFF timer has not expired yet. 0 RO
Table 209: MAC Hash Register 0–3 (Offset 0x470)
Address Offset MAC Hash Register 0: 0x470
Address Offset MAC Hash Register 1: 0x474
Address Offset MAC Hash Register 2: 0x478
Address Offset MAC Hash Register 3: 0x47C
Bit Field Description Init Access
31:0 Hash Value Hash Value for multicast destination address matching. 0 R/W
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