BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 255 Ethernet MAC Control Registers Document 5722-PG101-R
19 RSS TCP/IPv6 Hash Enable
(BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
When this bit is set, 4-tuple hashes are enabled for TCP
over IPv6 packets. This bit should be set to 0 if IPv6 RX is
disabled.
0R/W
Reserved (other devices) 0 RO
18 RSS IPv6 Hash Enable (BCM5722,
BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
When this bit is set, 2-tuple hashes are enabled for IPv6
packets. This bit should be set to 0 if IPv6 RX is disabled.
0R/W
Reserved (other devices) 0 RO
17 RSS TCP/IPv4 Hash Enable
(BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
When this bit is set, 4-tuple hashes are enabled for TCP
over IPv4 packets.
0R/W
Reserved (other devices) 0 RO
16 RSS IPv4 Hash Enable (BCM5722,
BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
When this bit is set, 2-tuple hashes are enabled for IPv4
packets.
0R/W
Reserved (other devices) 0 RO
15:13 Reserved – 0 RO
12 Extended Hash En Enable extended hash table size of 256 entries. By default,
the hash table supports 128 entries with a 7-bit CRC value.
0R/W
11 Filt_broadcast When set, reception of broadcast frames is disabled. 0 R/W
10 Keep VLAN Tag Diag Mode If set, forces Receive MAC to keep the VLAN tag in the
frame. This is for debugging purpose only and should be
reset during normal operation.
0R/W
9 No_CRC_Check No CRC check by receive MAC on incoming frames. Also,
allows the reception of packets received with RXERR on
the MII/GMII.
0R/W
8 Promiscuous Mode No source address or MC hashing checking will be
performed on incoming frames. All frames will be
accepted.
0R/W
7 Length Check If set, IEEE 802.2 length checking is done on LLC frames. 0 R/W
6 Accept Runts If set, the MAC accepts packets less than 64 bytes. 0 R/W
5 Reserved – 0 R/W
4 Keep Pause If set, the MAC forwards pause frame to host buffer. 0 R/W
3 Reserved – 0 RO
2 Enable Flow Control Enable automatic processing of IEEE 802.3x flow control
frames. This bit is orthogonal to the Keep Pause bit.
0R/W
1 Enable This bit controls whether the Receive MAC state machine
is active or not. When set to 0, it completes the current
operation and cleanly halts. Until it is completely halted, it
remains 1 when read.
0R/W
0 Reset When this bit is set to 1, the Receive MAC state machine
will be reset. This is a self-clearing bit.
0R/W
Table 207: Receive MAC Mode Register (Offset 0x468) (Cont.)
Bit Field Description Init Access
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