Broadcom BCM5722 - Table 179: Firmware Power Budgeting Register 3 (Offset 0 X180); Table 180: Firmware Power Budgeting Register 4 (Offset 0 X182)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe-Enhanced Capabilities Page 234
FIRMWARE POWER BUDGETING REGISTER 3 (OFFSET 0X180)
FIRMWARE POWER BUDGETING REGISTER 4 (OFFSET 0X182)
Table 179: Firmware Power Budgeting Register 3 (Offset 0x180)
Bit Field Description Init Access
15:13 Power Rail Specifies the power rail of the operating condition
12V (000)
3.3V (001)
1.8V (010)
Thermal (111)
0x0 RW from Internal CPU
Config RO
Memory RW
12:10 Type Specifies the type of the operating condition
PME Aux (000)
Auxiliary (001)
Idle (010)
Sustained (010)
Maximum (111)
0x0 RW from Internal CPU
Config RO
Memory RW
9:8 PM State Specifies the power management state of operating
condition—D0, D3
0x0 RW from Internal CPU
Config RO
Memory RW
7:0 Base Power Specifies in Watts the base power value in a given
operating conditions
0x0 RW from Internal CPU
Config RO
Memory RW
Table 180: Firmware Power Budgeting Register 4 (Offset 0x182)
Bit Field Description Init Access
15:13 Power Rail Specifies the power rail of the operating condition
12V (000)
3.3V (001)
1.8V (010)
Thermal (111)
0x0 RW from Internal CPU
Config RO
Memory RW
12:10 Type Specifies the type of the operating condition
PME Aux (000)
Auxiliary (001)
Idle (010)
Sustained (010)
Maximum (111)
0x0 RW from Internal CPU
Config RO
Memory RW
9:8 PM State Specifies the power management state of operating
condition—D0, D3
0x0 RW from Internal CPU
Config RO
Memory RW
7:0 Base Power Specifies in Watts the base power value in a given
operating conditions
0x0 RW from Internal CPU
Config RO
Memory RW