BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 171 Flow Control Document 5722-PG101-R
• Link partner sends a pause frame with pause_time = 0.
• Internal pause timer expires.
Transmit MAC
The transmit MAC is responsible for sending flow control frames. Software enables the transmit MAC to send flow control
frames by setting the Enable_Flow_Control bit in the Transmit_MAC_Mode register (see “Transmit MAC Mode Register
(Offset 0x45C)” on page 253). When software clears the Enable_Flow_Control bit, the transmit MAC will not generate flow
control frames. The MAC_RX_MBUF_Low_Water_Mark register value (see “MAC RX MBUF Low Watermark Register
(Offset 0x4414)” on page 308) triggers PAUSE frames to be transmitted when a threshold value is passed. Software may
alter the watermark to tune system performance.
As soon as PAUSE frame is transmitted, any incoming packet can be dropped, and the ifInDiscard counter in statistics (see
“MIB Network Interface Card Statistics” on page 56) will increase. When packet size is small (64 bytes) with 1000 Mbps,
more frames can be dropped. Even if the PAUSE frame is transmitted, Pause frames cannot inhibit MAC control frames.
Low Water Mark Maximum Receive Frames register (see “Low Watermark Maximum Receive Frames Register (Offset
0x504)” on page 258) control the number of good frames to receive after the RX MBUF Low Water Mark has been reached.
After the RX MAC receives this number of frames, it will drop subsequent incoming frames until the MBUF High Water Mark
is reached.
The IEEE 802.3 pause control frame contains a pause_time field. The BCM5722 Ethernet controller inserts a time quanta
into the pause_time field. Software should set the Enable_Long_Pause bit in the Transmit_MAC_Mode register to configure
long pause quanta. Clearing the Enable_Long_Pause bit will default the pause_time back to the shorter quanta. Table 86
shows the pause quanta based on the Enable_Long_Pause bit setting.
Receive MAC
The BCM5722 Ethernet controller receive MAC’s link partner may want to inhibit frame transmission until upstream
resources become available. The receive MAC must be configured to accept IEEE 802.3x pause frames (see Table 87).
Software should set the Enable_Flow_Control bit in the Receive_MAC_Mode_Control register to enable automatic
processing of flow control frames. If software clears the Enable_Flow_Control bit, IEEE 802.3x pause frames will be
discarded. The Keep_Pause bit in the Receive_MAC_Mode_Control register will instruct the RX engine to forward pause
frames to host memory. Software may be interested in setting this bit for debugging or promiscuous/sniffer configurations.
Passing pause frames to the host will increase DMA and protocol processing and consume available host buffers. The
receive MAC will filter pause control frames when the Keep_Pause bit is disabled.
Table 85: Transmit MAC Watermark Recommendation
Register Recommended Value
MAC_RX_MBUF_Low_Water_Mark 24
Table 86: Pause Quanta
Enable_Long_Pause Bit Pause_Time
DISABLED (0) 0x1FFF
ENABLED (1) 0xFFFF
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