Broadcom BCM5722 - Table 414: Transaction Configuration Register (0 X7 C04)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Registers Page 384
TRANSACTION CONFIGURATION REGISTER (0X7C04)
20 Disable UR Error When clear, this bit enables the DMA completion logic to check
for a completion packet with an Unsupported Request value.
0R/W
19 Disable RSV Error When clear, this bit enables the DMA completion logic to check
for a completion packet with a Reserved value.
0R/W
18 Enable MPS Check When set, this bit enables the DMA completion logic to check for
a TLP that violates the Maximum Payload Size requirement.
1R/W
17 Disable EP Error When clear, this bit enables the Transaction Layer to check for
Data Poisoning.
0R/W
16 Enable Bytecount Check When set, this bit enables the Transaction Layer's target to check
for byte count errors on incoming target accesses.
1R/W
15:14 Reserved – 0 R/W
13:11 DMA Read Traffic Class DMA Read Traffic Class. 0x0 R/W
10:8 DMA Write Traffic Class DMA Write Traffic Class. 0x0 R/W
7:6 Reserved – 0x0 R/W
5:0 Completion Timeout Programmable completion timeout in milliseconds. 0x2f R/W
Table 414: Transaction Configuration Register (0x7C04)
Bit Field Description Access Reset Init
31 Enable_Retry_Buffer_Timing_Mod Allows the Retry Buffer RAM Timing
Parameter to be modified if process timing
model was incorrect.
• 0 = Disable
• 1 = Enable new timing mode
RW Core 0
30 Reserved – RW Core 0
29 Enable 1-shot MSI (BCM5906 only) Write “1” to this bit to enable 1-shot MSI. If
one-shot MSI mode is enabled, the device
automatically disables all future interrupts and
goes into “during-interrupt” coalescing mode
after an MSI is generated. This is possible
because MSI is an edge-triggered interrupt
that does not require de-assertion by
software. Enabling one-shot MSI mode
reduces the overhead of the driver writing to
the interrupt mailbox in the interrupt handler.
The Interrupt is re-enabled in the normal way
by software writing to the interrupt mailbox.
RW Core 0
Reserved (all others) –
28 Reserved – RW Core 0
Table 413: TLP Control Register (Offset 0x7C00) (Cont.)
Bit Field Description Init Access