BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 385 PCIe Registers Document 5722-PG101-R
27 Select Core Clock Override This bit is used by software to allow it to
access PCIe register when the PCIe PLL
can’t lock after power up. This bit when set will
select the core clock to drive the PCIe logic.
This bit is accessible from Core Clock
whereas bit 28 of the Clock Control Register
is not accessible when there is no PCIe clock.
• 0 = Disable override
• 1 = Enable override
RW Core 0
26 CQ9139 Fix Enable Enable software to use the low priority
Interrupt Mailbox 0 to clear the interrupt.
• 0 = Disable Fix
• 1 = Enable Fix
RW Core 0
25 Enable cmpt Pwr Check Enable generation of Unexpected Completion
Error when the device receives a completion
packet during D3-Hot.
• 0 = Disable Checking
• 1 = Enable Checking
RW Core 0
24 Enable cq12696 Fix Enable generation of UR error when the
device receives a MR/MW during D3-Hot.
• 0 = Disable CQ12696 Fix
• 1 = Enable CQ12696 Fix
RW Core 0
23 Device Serial No. Override Enable the Device Serial No. registers at
offset 0x164 & 0x168 to be override with the
value at offset 0x60 and 0x64 when this bit is
set. In addition, this bit when set will prevent
the MAC Address from register 410 to be
copied over to offset 164 and 168. So this
means that FW needs to program the MAC
Address and then set this bit to 1 to prevent
the Device Serial No Registers from changing
after Firmware programs the MAC Address at
offset 410.
• 1 = Enable override or disable driver from
changing the value in register 410 to reflect
it in the Device Serial No. Register
• 0 = Disable override or enable driver to
change register 410 and reflect the content
of 410 in the Device Serial No. Register.
RW Core 0
22 Enable cq12455 Fix Enable Flat View Bug Fix
• 0 = Disable CQ12455 Fix
• 1 = Enable CQ12455 Fix
RW Core 0
21 Enable_TC_VC_Filtering_Check Enable TC_VC Filtering:
• 0 = Disable Filtering
• 1 = Enable Filtering
RW Core 1
20 Don’t_gen_hot_plug_msg Disable the device from generating Hot-Plug
Message when this bit is set
• 1 = Disable Generation
• 0 = Enable Generation
RW Core 1
Table 414: Transaction Configuration Register (0x7C04) (Cont.)
Bit Field Description Access Reset Init
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