BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 253 Ethernet MAC Control Registers Document 5722-PG101-R
TRANSMIT MAC MODE REGISTER (OFFSET 0X45C)
This register controls the transmit Ethernet interfaces.
TRANSMIT MAC STATUS REGISTER (OFFSET 0X460)
This register contains the status of the transmit Ethernet interface. Once the interface is initialized, this register is used to
determine the cause of a transmit error event. Bits 4 and 5 are ORed together, and an attention is generated if the attention
enable is set.
Table 204: Transmit MAC Mode Register (Offset 0x45C)
Bit Field Description Init Access
31:9 Reserved – X RO
8 Tx MAC State Machine
Lockup Fix Enable
(BCM5722, BCM5755,
BCM5755M,
BCM5756M, BCM5757
only)
Set this bit to 1 to enable the chip fix of Tx MAC FSM
Lockup Issue that happens due to corrupted TxMbuf.
0R/W
Reserved (other
devices)
–0RO
7 Link aware enable When set, transmission of packets by the MAC is enabled
only when link is up.
0R/W
6 Enable Long Pause When set, the PAUSE time value set in the transmitted
PAUSE frames is 0xFFFF. The default value for PAUSE
time is 0x1FFF.
0R/W
5 Enable Big Backoff MAC will use larger than normal back-off algorithm. 0 R/W
4 Enable Flow Control MAC will send 802.3x flow control frames. 0 R/W
3:2 Reserved – 0 RO
1 Enable This bit controls whether the Transmit MAC state machine
is active or not. When set to 0, it completes the current
operation and cleanly halts. Until it is completely halted, it
remains 1 when read.
0R/W
0 Reset When this bit is set to 1, the Transmit MAC state machine
will be reset. This is a self-clearing bit.
0R/W
Table 205: Transmit MAC Status Register (Offset 0x460)
Bit Field Description Init Access
31:6 Reserved – 0 RO
5 ODI Overrun Output Data Interface has overrun. 0 W2C
4 ODI Underrun Output Data Interface has underrun. 0 W2C
3 Link Up Link is up, if set. 0 RO
2 Sent XON An XON flow control frame was sent. 0 W2C
1 Sent XOFF An XOFF flow control frame was sent. 0 W2C
0 RX Currently XOFFed Received stopped due to flow control. 0 RO