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Broadcom BCM5722 - Device Configuration Shadow Register (Offset 0 X5104); Table 321: VCPU Status Register Fields (Offset 0 X5100); Table 322: RX RISC State Fields (Offset 0 X5104); Table 323: VCPU Holding Register (Offset 0 X5108)

Broadcom BCM5722
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Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Virtual CPU Registers (BCM5906 Only) Page 322
DEVICE CONFIGURATION SHADOW REGISTER (OFFSET 0X5104)
The device configuration shadow register reports the device configuration stored in the external EEPROM.
VIRTUAL CPU HOLDING REGISTER (OFFSET 0X5108)
This register is used only by the VCPU. It is used to store the temporary register value that the VCPU reads from other
registers. Some instructions are defined to update the holding register value.
VIRTUAL CPU DATA REGISTER (OFFSET 0X510C)
This register is used to store the configuration information that the VCPU reads from the EEPROM, such as VPD base
address and PXE base address. Some instructions are defined to update the data register value.
Table 321: VCPU Status Register Fields (Offset 0x5100)
Bit Field Description Init Access
25 VCPU Int All CPU attention bits are ORed and shown here. This register
can be used the for debugging purposes by EEPROM image
to perform bug patches and perform services.
0RO
24:17 Reserved 0 RO
16 ROM Sel When set to ‘1’, indicates that the program counter being
executed is in the internal ROM. Otherwise, the code being
executed is in the external EEPROM.
0RO
15:0 Program Counter Shows the address of the current instruction being executed. 0x0000 RO
Table 322: RX RISC State Fields (Offset 0x5104)
Bit Field Description Init Access
31:0 Configuration The VCPU copies the configuration field from the external
EEPROM into this register, so that software driver knows the
configuration and service supported by the device.
0R/W
Table 323: VCPU Holding Register (Offset 0x5108)
Bit Field Description Init Access
31:0 Hold_reg Used only by VCPU to store the temporary register value that the
VCPU reads from the other registers. Some instructions are
defined to update the hold register value.
0RO
Table 324: VCPU Data Register (Offset 0x510C)
Bit Field Description Init Access
31:0 data_reg Used as an operand of some opcodes. The VCPU adds this
register with the specified register, or compares it to the specified
register value.
0R/W

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