Broadcom BCM5722 - RX RISC Hardware Breakpoint Register (Offset 0 X5034); RX RISC Program Counter (Offset 0 X501 C); Table 318: RX RISC Hardware Breakpoint Register (Offset 0 X5034)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R RX RISC Registers Page 320
RX RISC PROGRAM COUNTER (OFFSET 0X501C)
The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur
at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in
the decode stage of the pipeline. Bits 31:2 are implemented. 1s written to bits 1:0 are ignored.
RX RISC HARDWARE BREAKPOINT REGISTER (OFFSET 0X5034)
This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in
this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated
in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on
and clear the Disable Hardware Breakpoint bit.
This register is also used to indicate the Progress Code for the ROM Loader.
Table 318: RX RISC Hardware Breakpoint Register (offset 0x5034)
Bit Field Description Init Access
31:2 Hardware Breakpoint Word address to break on. 0 R/W
1 Reserved – 0 RO
0 Disable Hardware
Breakpoint
When this bit is set, the Hardware Breakpoint is disabled. 1 R/W