Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R High-Priority Mailboxes Page 238
HIGH-PRIORITY MAILBOXES
These registers are called High-Priority Mailbox registers (or high-priority mailboxes). When a value is stored in the least
significant 32 bits of these registers, an event (known as a high-priority mailbox event) is generated to the RX RISC. To write
64 bits of a mailbox location, the upper 32 bits should be written to before the lower 32 bits.
INTERRUPT MAILBOX 0 REGISTER (OFFSET 0X200–0X207)
Note: High-Priority Mailboxes do not exist in the BCM5906 device.
Note: The high-priority mailbox registers are for host standard and flat modes only. For the indirect register
access mode, access the mailboxes via the low-priority mailboxes (see “Low-Priority Mailboxes” on page 324).
Table 186: High-Priority Mailbox Registers
Offset Registers
0x200–0x207 Interrupt Mailbox 0
0x208–0x267 Reserved
0x268–0x26f Receive BD Standard Producer Ring Producer Index
0x270–0x27f Reserved
0x280–0x287 Receive BD Return Ring 0 Consumer Index
0x288–0x28f Receive BD Return Ring 1 Consumer Index
0x290–0x297 Receive BD Return Ring 2 Consumer Index
0x298–0x29f Receive BD Return Ring 3 Consumer Index
0x2a0–0x2ff Reserved
0x300–0x307 Send BD Ring Host Producer Index
0x308–0x3ff Reserved
Table 187: High-Priority Mailbox Structure
Offset 31 24 23 0
0x00 Status Tag In ISR
0x04 Not used
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