Broadcom BCM5722 - Table 494: Receiver NOT_OK Counters (Phy_Addr = 0 X1, Reg_Addr = 14 H, Normal Operation); Table 495: Receiver NOT_OK Counters (Phy_Addr = 0 X1, Reg_Addr = 14 H, CRC Error Count Operation)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 433 Transceiver Registers Document 5722-PG101-R
RECEIVER NOT_OK COUNTERS (PHY_ADDR = 0X1, REG_ADDR = 14H)
Normal Operation (CRC Count Visibility = 0)
These counters increment each time the local or remote receiver enters the NOT_OK state (freezes at the maximum value
FFh) when the CRC Error Count Visibility bit of PHY Test Register 1 (see “PHY Test Register 1 (PHY_Addr = 0X1,
REG_Addr = 1EH)” on page 480) is clear. The counters automatically clear when read.
CRC Error Count Operation (CRC Count Visibility = 1)
The CRC error counter is merged into a 16-bit counter and increments each time the MAC Transceiver detects a CRC error
when the CRC Error Count Visibility bit of PHY Test Register 1 (see “PHY Test Register 1 (PHY_Addr = 0X1, REG_Addr =
1EH)” on page 480) is set. This counter freezes at the maximum value FFFFh. The counter automatically clears when read.
EXPANSION REGISTER ACCESS DATA (PHY_ADDR = 01H, REG_ADDR = 15H)
When the “Expansion Register Access Register (PHY_ADDR = 0x1, Reg_Addr = 17h)” on page 434 is enabled, this register
allows read/write access to the Expansion Register selected in the Expansion Register Access Register.
Table 494: Receiver NOT_OK Counters (PHY_Addr = 0x1, Reg_Addr = 14h, Normal Operation)
Bit Field Description Init Access
15:8 Local Receiver
NOT_OK Counter
Number of times local receiver was not OK since last
read (when PHY Test Register 1.
CRC_Error_Count_Visibility bit (see “PHY Test Register
1 (PHY_Addr = 0X1, REG_Addr = 1EH)” on page 480) is
clear).
00h R/W
7:0 Remote Receiver
NOT_OK Counter
Number of times the BCM5722 Ethernet controller
detected that the remote receiver was not OK since last
read (when PHY Test Register 1.
CRC_Error_Count_Visibility bit (see “PHY Test Register
1 (PHY_Addr = 0X1, REG_Addr = 1EH)” on page 480) is
clear).
00h R/W
Table 495: Receiver NOT_OK Counters (PHY_Addr = 0x1, Reg_Addr = 14h, CRC Error Count Operation)
Bit Field Description Init Access
15:0 CRC Error Counter This register becomes a 16-bit CRC error counter when
PHY Test Register 1.CRC_Error_Count_Visibility bit (see
“PHY Test Register 1 (PHY_Addr = 0X1, REG_Addr =
1EH)” on page 480) is set.
0000h R/W