Broadcom BCM5722 - Table 147: Link Capabilities Register (Offset 0 Xdc)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 219 PCIe Capabilities Document 5722-PG101-R
LINK CAPABILITIES REGISTER (OFFSET 0XDC)
Table 147: Link Capabilities Register (Offset 0xDC)
Bit Field Description Init Access
31:24 Port Number This value indicates the port number associated with
this link.
HWInit RO
23:19 Reserved – 0 RO
18 Clock Power
Management
0: clkreq not capable
1: clkreq capable
• 0 for BCM5755,
BCM5754,
BCM5787,
BCM5906,
BCM5722, and
BCM5757
• 1 for 5755M,
BCM5754M,
BCM5787M,
BCM5906M, and
BCM5756M
Host RO
FW R/W
17:15 L1 Exit Latency This value returns the L1 exit latency for this link. 6 R/W
a
a. This register is writable by the internal CPU.
14:12 L0s Exit Latency This value returns the L0s exit latency for this link.
• 0 = Less that 64 ns
• 1 = Less than 128 ns
• 2 = Less than 256 ns
• 3 = Less than 512 ns
• 4 = Less than 1 µs
• 5 = Less than 2 µs
• 6 = Less than 4 µs
• 7 = Greater than 4 µs
6R/Wa
11:10 Active State
Power
Management
Support
This value returns the supported ASPM states.
• 0 = Reserved
• 1 = L0s supported
• 2 = Reserved
• 3 = L0s and L1 supported
1R/W
a
9:4 Maximum Link
Width
This value returns the Maximum Link Width. Allowable
values are 1, 2, 4, 8, 12, 16, and 32 only. All other
values are reserved.
1R/W
a
3:0 Maximum Link
Speed
This value returns the Maximum Link Speed. 1 =
2.5 Gbps. All other values reserved.
1R/W
b
b. For BCM5906: R/W only by internal VCPU; not writable through PCI config space.