BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 177 Interrupt Processing Document 5722-PG101-R
Section 11: Interrupt Processing
HOST COALESCING
Interrupt coalescing (or interrupt moderation) is a common technique used by NIC vendors to increase the performance of
NICs. High-level descriptions of the benefits of interrupt coalescing can be found at:
• http://www.microsoft.com/HWDEV/devdes/optinic.htm
• http://support.microsoft.com/support/kb/articles/Q170/6/43.ASP
• http://msdn.microsoft.com/library/books/serverdg/networkadapterrequirements.htm
DESCRIPTION
The BCM5722 Ethernet controller supports the concept of host coalescing. Host coalescing controls when status information
is returned to the host, and when interrupts are generated. The BCM5722 Ethernet controller provides a number of SW
configurable registers that control when/how it updates the host with status information and how often it asserts an interrupt.
When the BCM5722 Ethernet controller has completed transmit or receive events, it updates a Status block in host memory.
This status block contains information that tells the host which transmit buffers have been DMAed by the NIC, and which
receive Buffer Descriptors (BDs) have been consumed by a newly arrived received packet. Normally, the host will check this
status block whenever an interrupt is generated. In addition, the host could also poll the status block to determine whether
or not it had been updated by the hardware since the last time the host had read the status block (this is called during
interrupt processing).
Whenever the NIC updates the status block, it will make a decision about whether to assert the interrupt line (INTA
) or not.
The BCM5722 Ethernet controller has special interrupt avoidance mechanisms that allow the host to tell the NIC not to
generate an interrupt when it writes a status block back to the host. In addition, there are also mechanisms that allow host
SW to control when and how often the status block is updated. For instance, the host could configure the NIC to only update
status block after it receives two packets, as opposed to one packet. These mechanisms are documented in more detail
below.
OPERATIONAL CHARACTERISTICS
The BCM5722 Ethernet controller DMAs the status block to host memory before a line interrupt or MSI is generated. The
host ISR reads the update bit at the top of the status block and checks whether this bit is set to 1 or not. When set to 1, the
updated bit of status block indicates the host that the status block has been refreshed by the MAC. The ISR must then write
to clear/de-assert this bit to dirty the status block, and then the ISR may proceed to read the updated producer/consumer
index pointers. This mechanism allows host system software to determine if the status block has been updated. Due to
various asynchronous timing issues (dependent upon platform) the ISR may occasionally see stale data. The ISR may either
spin and wait for the status block DMA to complete and explicitly flush the status block or just wait for the next line interrupt.
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