Broadcom BCM5722 - Table 102: bist Register (Offset 0 X0 F); Table 103: Base Address Register 1;2 (Offset 0 X10)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 193 PCI Configuration Registers Document 5722-PG101-R
BIST REGISTER (OFFSET 0X0F)
The 8-bit BIST register is used to initiate and report the results of any Built-In Self-Test. This device does not export BIST
results to this register. Therefore, this register defaults to 0x00 at power-on reset. Optionally, firmware could be developed
to execute a self-test and write the result into this register because this register may be written by the internal RISCs. This
register cannot be written via the host PCI interface.
BASE ADDRESS REGISTER 1/2 (OFFSET 0X10–0X17)
The 64-bit Base Address register is used to establish the memory space that the adapter requires within the system. Once
the system has determined the needs of all of the adapters, the operating system can be booted.
The device supports one 64-bit Base Address register which must be located in the host’s memory space. The other four
32-bit Base Address registers are not implemented and will each return 0x0000 when read.
Base Address register 1/2 is required for the device to function. It provides either a 64 KB or a 32 MB control region from
which the host can access the adapter. The size of the region is determined by the selected host View (bit 8 of PCI State
register).
Table 102: BIST Register (Offset 0x0F)
Bit Field Description Init Access
7:0 BIST Built-in self-test. 0 R/W
a
a. Not writable by PCI configuration access.
Table 103: Base Address Register 1/2 (Offset 0x10)
Bit Field Description Init Access
63:32 Extended Base
Address
High order address bits. X R/W
31:xx+1 Base Address Low order address bits. 0 R/W
xx-4 Size Indication Portion of the address bits that are used to indicate the size
of the PCI address map. These are all set to 0.
xx is equal
to 15 for Standard View, and to 24 for Flat View.
0RO
3 Prefetchable Indicates that there are no side effects on reads; the device
returns all bytes regardless of byte enables, and processor
writes can get merged. This bit is always 0.
0RO
2:1 Type Encoded with the following values:
• 00 = Located anywhere in 32-bit address space
• 01 = Reserved
• 10 = Located anywhere in 64-bit address space
• 11 = Reserved
The device is capable of being located anywhere within the
64-bit address space, so these bits are hard-coded to 10.
10 RO
0 Memory Space
Indicator
This bit is always 0. Base Address registers map to
Memory Space.
0RO