Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Basic Driver Interrupt Processing Flow Page 184
INTERRUPT PROCEDURE
1. Acknowledge interrupt. Write a nonzero value (i.e., value = 1) to the interrupt mailbox 0 (see “Interrupt Mailbox 0 Register
(Offset 0x200–0x207)” on page 238 for host standard and flat modes and “Interrupt Mailbox 0 Register (Offset
0x5800–0x5807)” on page 325 for indirect mode) to indicate that the driver is currently processing the interrupt. This
step disables device interrupts except during interrupt feature.
2. Read and save the value of the Status Tag field of the Status Block (see “Status Block” on page 53).
3. Claim interrupt. Determine if the BCM5722 Ethernet controller action is required. Read the Updated bit of the status word
(see Table 27 on page 57). If the Updated bit is asserted, then the host coalescing engine has updated the status block.
4. Clear the Updated bit of the status word (see Table 27 on page 57). This indicates that the host driver either has or will
touch the status block. If a during interrupt event is driven, the host driver can examine the Updated bit to determine if
a fresh status block has been moved to host memory space.
5. Check for RX traffic.
• Loop through enabled RX Return Rings (1 to 16).
• Check for difference between RX Return Ring Producer index (Status block) and RX Return Ring Consumer index
(value written to mailbox on previous call) are the number of frames to process for RX Return Ring.
• Process the packet.
• Update the RX Return Ring consumer pointer in each mailbox for new RX frames.
6. Check for TX completes.
• Loop through enabled TX Send Rings.
• Check for difference between previous consumer index (software kept) and current consumer index in the status
block. These are the TX BDs which can be made available to next send operation.
• Update the previous consumer index (i.e., next call) to the value of the status block consumer index.
7. Compare the current value of the Status Tag to the saved value of the Status Tag. Flush status block (i.e., force update
of status blocks cached by PCI bridge).
• Read interrupt mailbox (see “Interrupt Mailbox 0 Register (Offset 0x200–0x207)” on page 238 for host standard and
flat modes and “Interrupt Mailbox 0 Register (Offset 0x5800–0x5807)” on page 325 for indirect mode).
• Check the Updated bit in the status word (see Table 27 on page 57) located in the status block. If the Updated bit is
asserted, then new data has been DMAed to the host. Repeat steps 5 and 6.
8. Check the Error bit in status word (optional, see Table 27 on page 57). The driver may check the state machine/FTQ
status registers for various attentions.
9. Enable interrupts. When Status Tagged Status Mode bit of the Miscellaneous Host Control register (see“Miscellaneous
Host Control Register (Offset 0x68)” on page 204) is set to 1, then write the saved Status Tag to the upper 8 bits of
Interrupt Mailbox 0, and 0 to the remaining bits (23 down to 0) to indicate that the ISR is done processing RX/TX.
Otherwise, write 0 to Interrupt Mailbox 0 register. This step also clears existing interrupts.
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