Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Hardware Architecture Page 14
Section 3: Hardware Architecture
THEORY OF OPERATION
Figure 3 shows the major functional blocks and interfaces of the BCM5722 Ethernet controllers. There are two packet flows:
MAC-transmit and receive. The device’s DMA engine bus-masters packets from host memory to device local storage, and
vice-versa. The host bus interface is compliant with PCIe standards. The RX MAC moves packets from the integrated PHY
into device internal memory. All incoming packets are checked against a set of QOS rules and then categorized. When a
packet is transmitted, the TX MAC moves data from device internal memory to the PHY. Both flows operate independently
of each other in full-duplex mode. An on-chip RISC processor is provided for running value-added firmware that can be used
for custom frame processing. The on-chip RISC operates independently of all the architectural blocks; essentially, RISC is
available for the auxiliary processing of data streams.
Figure 3: Functional Block Diagram
Receive
MAC
Rx
FIFO
Transmit
MAC
Tx
FIFO
Statistics
Rule
Check
Memory
Arbiter
Tx Frame Buffer
Memory
Send BD RING
Boot
Processor
Boot ROM
Frame Buffer
Manager
Queue
Memory
Read
DMA
Read
FIFO
Write
DMA
Write
FIFO
Registers
SSRAM Control
SSRAM
Interface
PCIe Bu
Ring Controllers
Host Coalescing
Queue Management
Receive
GMII
Transmit
GMII
LED
Control
PLL
LED Signals
125-MHz Clock
Receive BD RING
DMA Descriptor
Config
EEPROM Control
NVRAM
Interface
Physical Layer
Transceiver
System Management
Control
SMBus
PCIe
Rx Frame Buffer
Memory/RISC
Scratch Pad Memory
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