Broadcom BCM5722 - Table 183: Firmware Power Budgeting Register 7 (Offset 0 X188); Table 184: Firmware Power Budgeting Register 8 (Offset 0 X18 A)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe-Enhanced Capabilities Page 236
FIRMWARE POWER BUDGETING REGISTER 7 (OFFSET 0X188)
FIRMWARE POWER BUDGETING REGISTER 8 (OFFSET 0X18A)
Table 183: Firmware Power Budgeting Register 7 (Offset 0x188)
Bit Field Description Init Access
15:13 Power Rail Specifies the power rail of the operating condition
12V (000)
3.3V (001)
1.8V (010)
Thermal (111)
0x0 RW from Internal CPU
Config RO
Memory RW
12:10 Type Specifies the type of the operating condition
PME Aux (000)
Auxiliary (001)
Idle (010)
Sustained (010)
Maximum (111)
0x0 RW from Internal CPU
Config RO
Memory RW
9:8 PM State Specifies the power management state of operating
condition—D0, D3
0x0 RW from Internal CPU
Config RO
Memory RW
7:0 Base Power Specifies in Watts the base power value in a given
operating conditions
0x0 RW from Internal CPU
Config RO
Memory RW
Table 184: Firmware Power Budgeting Register 8 (Offset 0x18A)
Bit Field Description Init Access
15:13 Power Rail Specifies the power rail of the operating condition
12V (000)
3.3V (001)
1.8V (010)
Thermal (111)
0x0 RW from Internal CPU
Config RO
Memory RW
12:10 Type Specifies the type of the operating condition
PME Aux (000)
Auxiliary (001)
Idle (010)
Sustained (010)
Maximum (111)
0x0 RW from Internal CPU
Config RO
Memory RW
9:8 PM State Specifies the power management state of operating
condition—D0, D3
0x0 RW from Internal CPU
Config RO
Memory RW
7:0 Base Power Specifies in Watts the base power value in a given
operating conditions
0x0 RW from Internal CPU
Config RO
Memory RW