Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Wake-on-LAN Registers Page 346
WOL STATE MACHINE STATUS REGISTER (OFFSET 0X6888)
12:11 SD_delay_cfg This is the amount of the delay.
• 00 = 0
• 01 = 50 µs
• 10 = 150 µs
• 11 = 250 µs
0R/W
10 Power_avail When set to 1, it indicates the main power is available. 0 R/W
9 PHY_bypass When set to 1, it indicates that it is emulation (IKOS)
mode.
0R/W
8 Lom_enable When set to 1, LOM is enabled. 0 R/W
7:3 Reserved – 0 R/W
2 WOL_done 2 When set to 1, WOL finishes its operations. 0 R/W
1 WOL_start 1 When set to 1, WOL state machines starts. 0 R/W
0 WOL_10 When set to 1, WOL is 10 Mbit only. When set to 0, WOL
is 100 Mbit.
0R/W
Table 359: WOL State Machine Status Register (Offset 0x6888)
Bit Field Description Init Access
31:29 Reserved – 0 RO
28:24 SD_state[4:0] ShutDown control state machine value 0 RO
23:20 Reserved – 0 RO
19:16 SC_state[3:0] Slow_Clock control state machine value 0 RO
15:13 Reserved – 0 RO
12:8 SW_state[4:0] Setup_Wol control state machine value 0 RO
7:3 Reserved – 0 RO
2:0 Wol_state[2:0] WOL top control state machine value 0 RO
Table 358: WOL Config Register (Offset 0x6884) (Cont.)
Bit Field Description Init Access