Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R General Control Registers Page 338
RX-RISC EVENT REGISTER (OFFSET 0X6810)
The RX-RISC uses the following event register. Software events are set by writing a one to the bit. The software event, timer
event, and TX-RISC event are reset by writing a zero to the bit. Other events are based on hardware events and cannot be
affected directly by the RISC processor.
Note: The version of Rx-RISC Event Register shown in Table 346 applies to BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757, BCM5754, BCM5787 only.
Table 346: RX-RISC Event Register (Offset 0x6810)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757,
BCM5754, BCM5787 Only
Bit Field Description Init Access
31 SW Event 13 SW Event 13 is set. 0 R/W
30 SW Event 12 SW Event 12 is set. 0 R/W
29 Timer Timer reference reached. 0 R/W
28 SW Event 11 SW Event 11 is set. 0 R/W
27 Flow Attn Flow attention. 0 RO
26 RX-CPU Attn RX-RISC needs attention. 0 R/W
25 MAC Attn MAC needs attention. 0 RO
24 TX-CPU Attn TX-RISC needs attention. 0 RO
23 SW Event 10 SW Event 10 is set. 0 R/W
22 High-priority Mailbox First 32 Mailbox registers have been updated. 0 RO
21 Low-priority Mailbox Last 32 Mailbox registers have been updated. 0 RO
20 DMA Attn A DMA channel needs attention. 0 RO
19 SW Event 9 SW Event 9 is set. 0 R/W
18 High DMA RD (other
devices)
High Priority DMA read FTQ has stalled. 0 RO
17 High DMA WR (all other
devices)
High Priority DMA write FTQ has stalled. 0 RO
16 SW Event 8 SW Event 8 is set. 0 R/W
15 Host Coalescing The host coalescing FTQ has stalled. 0 RO
14 SW Event 7 SW Event 7 is set. 0 R/W
13 Recv Data Comp (Post
DMA)
Receive data completion FTQ has stalled. 0 RO
12 SW Event 6 SW Event 6 is set. 0 R/W
11 RX SW Queue Event Receive Software Queue Event. 0 R/W
10 DMA RD Normal Priority DMA read FTQ has stalled. 0 RO
9 DMA WR Normal Priority DMA write FTQ has stalled. 0 RO
8 Recv Data Init (Pre DMA) Receive Data and Receive BD initiator FTQ has stalled. 0 RO
7 SW Event 5 SW Event 5 is set. 0 R/W
6 Recv BD Comp Receive BD completion FTQ has stalled. 0 RO
5 SW Event 4 SW Event 4 is set. 0 R/W
4 Recv List Selector Recv list selector is nonzero. 0 RO
3 SW Event 3 SW Event 3 is set. 0 R/W
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