BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 209 Broadcom Vendor-Specific Capabilities Document 5722-PG101-R
REGISTER BASE ADDRESS REGISTER (OFFSET 0X78)
The Register Base Address register defines the device local address of a register. The data pointed to by this location is
read or written using the Register Data register.
The following steps describe how to use the Register Base Address/Register Data registers.
1. Enable indirect mode by setting the Enable Indirect Access bit of the Miscellaneous Host Control register (see
“Miscellaneous Host Control Register (Offset 0x68)” on page 204).
2. Write the address of the Register that you would like to access to the Register Base Address register (offset 0x78–0x7B).
The least significant two bits of the Register Base Address register will always be ignored since Registers are naturally
word (32-bit) aligned. To allow access to all of the BCM5722 Ethernet controller registers, the range of the Register Base
Address register is [17:2].
3. To write the Register pointed to by the Register Base Address register, write the 32-bit data to the Register Data register.
At least one byte enable in the word to be written from the PCI-based Host must be asserted for the write to occur,
otherwise, the write will be ignored.
4. To read the Register pointed to by the Register Base Address register, read the 32-bit data from the Register Data
register.
Table 130: Register Base Address Register (Offset 0x78)
Bit Field Description Init Access
31:18 Reserved Reserved for testing or future use. X RO
17:2 Register Base Addr Local controller address of a register than can be written or
read by writing to the Register Data Register.
0 on hard
reset.
R/W
1:0 Reserved Reserved for testing or future use. X RO
Note: When using indirect register access, Broadcom recommends that the host software access the Register
Base Address register (offset 0x78) and the Register Data register (offset 0x80) using PCI configuration cycles
rather than memory-mapped I/O (i.e., accessing the PCI configuration registers at offsets 0x78 and 0x80 by
memory addresses enabled through the PCI BAR registers). If memory-mapped I/O access is used, every register
write must be followed by a read from the same register to guarantee that the posted write buffer is flushed.
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